mirror of https://github.com/ARMmbed/mbed-os.git
160 lines
7.2 KiB
C
160 lines
7.2 KiB
C
/***************************************************************************//**
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* \file cyip_pdm.h
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*
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* \brief
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* PDM IP definitions
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*
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* \note
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* Generator version: 1.2.0.117
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* Database revision: rev#1034984
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*
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********************************************************************************
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* \copyright
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* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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*******************************************************************************/
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#ifndef _CYIP_PDM_H_
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#define _CYIP_PDM_H_
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#include "cyip_headers.h"
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/*******************************************************************************
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* PDM
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*******************************************************************************/
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#define PDM_SECTION_SIZE 0x00001000UL
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/**
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* \brief PDM registers (PDM)
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*/
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typedef struct {
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__IOM uint32_t CTL; /*!< 0x00000000 Control */
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__IM uint32_t RESERVED[3];
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__IOM uint32_t CLOCK_CTL; /*!< 0x00000010 Clock control */
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__IOM uint32_t MODE_CTL; /*!< 0x00000014 Mode control */
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__IOM uint32_t DATA_CTL; /*!< 0x00000018 Data control */
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__IM uint32_t RESERVED1;
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__IOM uint32_t CMD; /*!< 0x00000020 Command */
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__IM uint32_t RESERVED2[7];
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__IOM uint32_t TR_CTL; /*!< 0x00000040 Trigger control */
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__IM uint32_t RESERVED3[175];
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__IOM uint32_t RX_FIFO_CTL; /*!< 0x00000300 RX FIFO control */
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__IM uint32_t RX_FIFO_STATUS; /*!< 0x00000304 RX FIFO status */
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__IM uint32_t RX_FIFO_RD; /*!< 0x00000308 RX FIFO read */
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__IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x0000030C RX FIFO silent read */
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__IM uint32_t RESERVED4[764];
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__IOM uint32_t INTR; /*!< 0x00000F00 Interrupt register */
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__IOM uint32_t INTR_SET; /*!< 0x00000F04 Interrupt set register */
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__IOM uint32_t INTR_MASK; /*!< 0x00000F08 Interrupt mask register */
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__IM uint32_t INTR_MASKED; /*!< 0x00000F0C Interrupt masked register */
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} PDM_Type; /*!< Size = 3856 (0xF10) */
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/* PDM.CTL */
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#define PDM_CTL_PGA_R_Pos 0UL
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#define PDM_CTL_PGA_R_Msk 0xFUL
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#define PDM_CTL_PGA_L_Pos 8UL
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#define PDM_CTL_PGA_L_Msk 0xF00UL
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#define PDM_CTL_SOFT_MUTE_Pos 16UL
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#define PDM_CTL_SOFT_MUTE_Msk 0x10000UL
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#define PDM_CTL_STEP_SEL_Pos 17UL
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#define PDM_CTL_STEP_SEL_Msk 0x20000UL
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#define PDM_CTL_ENABLED_Pos 31UL
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#define PDM_CTL_ENABLED_Msk 0x80000000UL
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/* PDM.CLOCK_CTL */
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#define PDM_CLOCK_CTL_CLK_CLOCK_DIV_Pos 0UL
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#define PDM_CLOCK_CTL_CLK_CLOCK_DIV_Msk 0x3UL
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#define PDM_CLOCK_CTL_MCLKQ_CLOCK_DIV_Pos 4UL
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#define PDM_CLOCK_CTL_MCLKQ_CLOCK_DIV_Msk 0x30UL
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#define PDM_CLOCK_CTL_CKO_CLOCK_DIV_Pos 8UL
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#define PDM_CLOCK_CTL_CKO_CLOCK_DIV_Msk 0xF00UL
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#define PDM_CLOCK_CTL_SINC_RATE_Pos 16UL
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#define PDM_CLOCK_CTL_SINC_RATE_Msk 0x7F0000UL
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/* PDM.MODE_CTL */
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#define PDM_MODE_CTL_PCM_CH_SET_Pos 0UL
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#define PDM_MODE_CTL_PCM_CH_SET_Msk 0x3UL
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#define PDM_MODE_CTL_SWAP_LR_Pos 2UL
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#define PDM_MODE_CTL_SWAP_LR_Msk 0x4UL
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#define PDM_MODE_CTL_S_CYCLES_Pos 8UL
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#define PDM_MODE_CTL_S_CYCLES_Msk 0x700UL
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#define PDM_MODE_CTL_CKO_DELAY_Pos 16UL
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#define PDM_MODE_CTL_CKO_DELAY_Msk 0x70000UL
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#define PDM_MODE_CTL_HPF_GAIN_Pos 24UL
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#define PDM_MODE_CTL_HPF_GAIN_Msk 0xF000000UL
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#define PDM_MODE_CTL_HPF_EN_N_Pos 28UL
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#define PDM_MODE_CTL_HPF_EN_N_Msk 0x10000000UL
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/* PDM.DATA_CTL */
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#define PDM_DATA_CTL_WORD_LEN_Pos 0UL
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#define PDM_DATA_CTL_WORD_LEN_Msk 0x3UL
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#define PDM_DATA_CTL_BIT_EXTENSION_Pos 8UL
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#define PDM_DATA_CTL_BIT_EXTENSION_Msk 0x100UL
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/* PDM.CMD */
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#define PDM_CMD_STREAM_EN_Pos 0UL
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#define PDM_CMD_STREAM_EN_Msk 0x1UL
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/* PDM.TR_CTL */
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#define PDM_TR_CTL_RX_REQ_EN_Pos 16UL
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#define PDM_TR_CTL_RX_REQ_EN_Msk 0x10000UL
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/* PDM.RX_FIFO_CTL */
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#define PDM_RX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL
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#define PDM_RX_FIFO_CTL_TRIGGER_LEVEL_Msk 0xFFUL
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#define PDM_RX_FIFO_CTL_CLEAR_Pos 16UL
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#define PDM_RX_FIFO_CTL_CLEAR_Msk 0x10000UL
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#define PDM_RX_FIFO_CTL_FREEZE_Pos 17UL
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#define PDM_RX_FIFO_CTL_FREEZE_Msk 0x20000UL
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/* PDM.RX_FIFO_STATUS */
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#define PDM_RX_FIFO_STATUS_USED_Pos 0UL
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#define PDM_RX_FIFO_STATUS_USED_Msk 0xFFUL
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#define PDM_RX_FIFO_STATUS_RD_PTR_Pos 16UL
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#define PDM_RX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL
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#define PDM_RX_FIFO_STATUS_WR_PTR_Pos 24UL
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#define PDM_RX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL
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/* PDM.RX_FIFO_RD */
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#define PDM_RX_FIFO_RD_DATA_Pos 0UL
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#define PDM_RX_FIFO_RD_DATA_Msk 0xFFFFFFFFUL
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/* PDM.RX_FIFO_RD_SILENT */
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#define PDM_RX_FIFO_RD_SILENT_DATA_Pos 0UL
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#define PDM_RX_FIFO_RD_SILENT_DATA_Msk 0xFFFFFFFFUL
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/* PDM.INTR */
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#define PDM_INTR_RX_TRIGGER_Pos 16UL
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#define PDM_INTR_RX_TRIGGER_Msk 0x10000UL
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#define PDM_INTR_RX_NOT_EMPTY_Pos 18UL
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#define PDM_INTR_RX_NOT_EMPTY_Msk 0x40000UL
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#define PDM_INTR_RX_OVERFLOW_Pos 21UL
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#define PDM_INTR_RX_OVERFLOW_Msk 0x200000UL
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#define PDM_INTR_RX_UNDERFLOW_Pos 22UL
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#define PDM_INTR_RX_UNDERFLOW_Msk 0x400000UL
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/* PDM.INTR_SET */
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#define PDM_INTR_SET_RX_TRIGGER_Pos 16UL
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#define PDM_INTR_SET_RX_TRIGGER_Msk 0x10000UL
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#define PDM_INTR_SET_RX_NOT_EMPTY_Pos 18UL
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#define PDM_INTR_SET_RX_NOT_EMPTY_Msk 0x40000UL
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#define PDM_INTR_SET_RX_OVERFLOW_Pos 21UL
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#define PDM_INTR_SET_RX_OVERFLOW_Msk 0x200000UL
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#define PDM_INTR_SET_RX_UNDERFLOW_Pos 22UL
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#define PDM_INTR_SET_RX_UNDERFLOW_Msk 0x400000UL
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/* PDM.INTR_MASK */
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#define PDM_INTR_MASK_RX_TRIGGER_Pos 16UL
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#define PDM_INTR_MASK_RX_TRIGGER_Msk 0x10000UL
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#define PDM_INTR_MASK_RX_NOT_EMPTY_Pos 18UL
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#define PDM_INTR_MASK_RX_NOT_EMPTY_Msk 0x40000UL
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#define PDM_INTR_MASK_RX_OVERFLOW_Pos 21UL
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#define PDM_INTR_MASK_RX_OVERFLOW_Msk 0x200000UL
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#define PDM_INTR_MASK_RX_UNDERFLOW_Pos 22UL
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#define PDM_INTR_MASK_RX_UNDERFLOW_Msk 0x400000UL
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/* PDM.INTR_MASKED */
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#define PDM_INTR_MASKED_RX_TRIGGER_Pos 16UL
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#define PDM_INTR_MASKED_RX_TRIGGER_Msk 0x10000UL
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#define PDM_INTR_MASKED_RX_NOT_EMPTY_Pos 18UL
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#define PDM_INTR_MASKED_RX_NOT_EMPTY_Msk 0x40000UL
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#define PDM_INTR_MASKED_RX_OVERFLOW_Pos 21UL
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#define PDM_INTR_MASKED_RX_OVERFLOW_Msk 0x200000UL
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#define PDM_INTR_MASKED_RX_UNDERFLOW_Pos 22UL
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#define PDM_INTR_MASKED_RX_UNDERFLOW_Msk 0x400000UL
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#endif /* _CYIP_PDM_H_ */
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/* [] END OF FILE */
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