mirror of https://github.com/ARMmbed/mbed-os.git
279 lines
14 KiB
C
279 lines
14 KiB
C
/***************************************************************************//**
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* \file cyip_i2s.h
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*
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* \brief
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* I2S IP definitions
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*
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* \note
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* Generator version: 1.2.0.117
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* Database revision: rev#1034984
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*
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********************************************************************************
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* \copyright
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* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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*******************************************************************************/
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#ifndef _CYIP_I2S_H_
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#define _CYIP_I2S_H_
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#include "cyip_headers.h"
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/*******************************************************************************
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* I2S
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*******************************************************************************/
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#define I2S_SECTION_SIZE 0x00001000UL
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/**
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* \brief I2S registers (I2S)
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*/
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typedef struct {
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__IOM uint32_t CTL; /*!< 0x00000000 Control */
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__IM uint32_t RESERVED[3];
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__IOM uint32_t CLOCK_CTL; /*!< 0x00000010 Clock control */
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__IM uint32_t RESERVED1[3];
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__IOM uint32_t CMD; /*!< 0x00000020 Command */
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__IM uint32_t RESERVED2[7];
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__IOM uint32_t TR_CTL; /*!< 0x00000040 Trigger control */
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__IM uint32_t RESERVED3[15];
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__IOM uint32_t TX_CTL; /*!< 0x00000080 Transmitter control */
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__IOM uint32_t TX_WATCHDOG; /*!< 0x00000084 Transmitter watchdog */
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__IM uint32_t RESERVED4[6];
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__IOM uint32_t RX_CTL; /*!< 0x000000A0 Receiver control */
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__IOM uint32_t RX_WATCHDOG; /*!< 0x000000A4 Receiver watchdog */
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__IM uint32_t RESERVED5[86];
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__IOM uint32_t TX_FIFO_CTL; /*!< 0x00000200 TX FIFO control */
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__IM uint32_t TX_FIFO_STATUS; /*!< 0x00000204 TX FIFO status */
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__OM uint32_t TX_FIFO_WR; /*!< 0x00000208 TX FIFO write */
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__IM uint32_t RESERVED6[61];
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__IOM uint32_t RX_FIFO_CTL; /*!< 0x00000300 RX FIFO control */
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__IM uint32_t RX_FIFO_STATUS; /*!< 0x00000304 RX FIFO status */
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__IM uint32_t RX_FIFO_RD; /*!< 0x00000308 RX FIFO read */
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__IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x0000030C RX FIFO silent read */
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__IM uint32_t RESERVED7[764];
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__IOM uint32_t INTR; /*!< 0x00000F00 Interrupt register */
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__IOM uint32_t INTR_SET; /*!< 0x00000F04 Interrupt set register */
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__IOM uint32_t INTR_MASK; /*!< 0x00000F08 Interrupt mask register */
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__IM uint32_t INTR_MASKED; /*!< 0x00000F0C Interrupt masked register */
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} I2S_Type; /*!< Size = 3856 (0xF10) */
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/* I2S.CTL */
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#define I2S_CTL_TX_ENABLED_Pos 30UL
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#define I2S_CTL_TX_ENABLED_Msk 0x40000000UL
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#define I2S_CTL_RX_ENABLED_Pos 31UL
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#define I2S_CTL_RX_ENABLED_Msk 0x80000000UL
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/* I2S.CLOCK_CTL */
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#define I2S_CLOCK_CTL_CLOCK_DIV_Pos 0UL
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#define I2S_CLOCK_CTL_CLOCK_DIV_Msk 0x3FUL
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#define I2S_CLOCK_CTL_CLOCK_SEL_Pos 8UL
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#define I2S_CLOCK_CTL_CLOCK_SEL_Msk 0x100UL
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/* I2S.CMD */
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#define I2S_CMD_TX_START_Pos 0UL
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#define I2S_CMD_TX_START_Msk 0x1UL
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#define I2S_CMD_TX_PAUSE_Pos 8UL
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#define I2S_CMD_TX_PAUSE_Msk 0x100UL
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#define I2S_CMD_RX_START_Pos 16UL
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#define I2S_CMD_RX_START_Msk 0x10000UL
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/* I2S.TR_CTL */
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#define I2S_TR_CTL_TX_REQ_EN_Pos 0UL
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#define I2S_TR_CTL_TX_REQ_EN_Msk 0x1UL
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#define I2S_TR_CTL_RX_REQ_EN_Pos 16UL
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#define I2S_TR_CTL_RX_REQ_EN_Msk 0x10000UL
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/* I2S.TX_CTL */
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#define I2S_TX_CTL_B_CLOCK_INV_Pos 3UL
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#define I2S_TX_CTL_B_CLOCK_INV_Msk 0x8UL
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#define I2S_TX_CTL_CH_NR_Pos 4UL
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#define I2S_TX_CTL_CH_NR_Msk 0x70UL
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#define I2S_TX_CTL_MS_Pos 7UL
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#define I2S_TX_CTL_MS_Msk 0x80UL
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#define I2S_TX_CTL_I2S_MODE_Pos 8UL
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#define I2S_TX_CTL_I2S_MODE_Msk 0x300UL
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#define I2S_TX_CTL_WS_PULSE_Pos 10UL
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#define I2S_TX_CTL_WS_PULSE_Msk 0x400UL
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#define I2S_TX_CTL_OVHDATA_Pos 12UL
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#define I2S_TX_CTL_OVHDATA_Msk 0x1000UL
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#define I2S_TX_CTL_WD_EN_Pos 13UL
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#define I2S_TX_CTL_WD_EN_Msk 0x2000UL
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#define I2S_TX_CTL_CH_LEN_Pos 16UL
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#define I2S_TX_CTL_CH_LEN_Msk 0x70000UL
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#define I2S_TX_CTL_WORD_LEN_Pos 20UL
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#define I2S_TX_CTL_WORD_LEN_Msk 0x700000UL
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#define I2S_TX_CTL_SCKO_POL_Pos 24UL
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#define I2S_TX_CTL_SCKO_POL_Msk 0x1000000UL
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#define I2S_TX_CTL_SCKI_POL_Pos 25UL
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#define I2S_TX_CTL_SCKI_POL_Msk 0x2000000UL
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/* I2S.TX_WATCHDOG */
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#define I2S_TX_WATCHDOG_WD_COUNTER_Pos 0UL
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#define I2S_TX_WATCHDOG_WD_COUNTER_Msk 0xFFFFFFFFUL
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/* I2S.RX_CTL */
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#define I2S_RX_CTL_B_CLOCK_INV_Pos 3UL
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#define I2S_RX_CTL_B_CLOCK_INV_Msk 0x8UL
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#define I2S_RX_CTL_CH_NR_Pos 4UL
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#define I2S_RX_CTL_CH_NR_Msk 0x70UL
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#define I2S_RX_CTL_MS_Pos 7UL
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#define I2S_RX_CTL_MS_Msk 0x80UL
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#define I2S_RX_CTL_I2S_MODE_Pos 8UL
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#define I2S_RX_CTL_I2S_MODE_Msk 0x300UL
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#define I2S_RX_CTL_WS_PULSE_Pos 10UL
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#define I2S_RX_CTL_WS_PULSE_Msk 0x400UL
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#define I2S_RX_CTL_WD_EN_Pos 13UL
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#define I2S_RX_CTL_WD_EN_Msk 0x2000UL
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#define I2S_RX_CTL_CH_LEN_Pos 16UL
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#define I2S_RX_CTL_CH_LEN_Msk 0x70000UL
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#define I2S_RX_CTL_WORD_LEN_Pos 20UL
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#define I2S_RX_CTL_WORD_LEN_Msk 0x700000UL
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#define I2S_RX_CTL_BIT_EXTENSION_Pos 23UL
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#define I2S_RX_CTL_BIT_EXTENSION_Msk 0x800000UL
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#define I2S_RX_CTL_SCKO_POL_Pos 24UL
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#define I2S_RX_CTL_SCKO_POL_Msk 0x1000000UL
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#define I2S_RX_CTL_SCKI_POL_Pos 25UL
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#define I2S_RX_CTL_SCKI_POL_Msk 0x2000000UL
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/* I2S.RX_WATCHDOG */
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#define I2S_RX_WATCHDOG_WD_COUNTER_Pos 0UL
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#define I2S_RX_WATCHDOG_WD_COUNTER_Msk 0xFFFFFFFFUL
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/* I2S.TX_FIFO_CTL */
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#define I2S_TX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL
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#define I2S_TX_FIFO_CTL_TRIGGER_LEVEL_Msk 0xFFUL
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#define I2S_TX_FIFO_CTL_CLEAR_Pos 16UL
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#define I2S_TX_FIFO_CTL_CLEAR_Msk 0x10000UL
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#define I2S_TX_FIFO_CTL_FREEZE_Pos 17UL
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#define I2S_TX_FIFO_CTL_FREEZE_Msk 0x20000UL
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/* I2S.TX_FIFO_STATUS */
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#define I2S_TX_FIFO_STATUS_USED_Pos 0UL
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#define I2S_TX_FIFO_STATUS_USED_Msk 0x1FFUL
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#define I2S_TX_FIFO_STATUS_RD_PTR_Pos 16UL
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#define I2S_TX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL
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#define I2S_TX_FIFO_STATUS_WR_PTR_Pos 24UL
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#define I2S_TX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL
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/* I2S.TX_FIFO_WR */
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#define I2S_TX_FIFO_WR_DATA_Pos 0UL
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#define I2S_TX_FIFO_WR_DATA_Msk 0xFFFFFFFFUL
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/* I2S.RX_FIFO_CTL */
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#define I2S_RX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL
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#define I2S_RX_FIFO_CTL_TRIGGER_LEVEL_Msk 0xFFUL
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#define I2S_RX_FIFO_CTL_CLEAR_Pos 16UL
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#define I2S_RX_FIFO_CTL_CLEAR_Msk 0x10000UL
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#define I2S_RX_FIFO_CTL_FREEZE_Pos 17UL
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#define I2S_RX_FIFO_CTL_FREEZE_Msk 0x20000UL
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/* I2S.RX_FIFO_STATUS */
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#define I2S_RX_FIFO_STATUS_USED_Pos 0UL
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#define I2S_RX_FIFO_STATUS_USED_Msk 0x1FFUL
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#define I2S_RX_FIFO_STATUS_RD_PTR_Pos 16UL
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#define I2S_RX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL
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#define I2S_RX_FIFO_STATUS_WR_PTR_Pos 24UL
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#define I2S_RX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL
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/* I2S.RX_FIFO_RD */
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#define I2S_RX_FIFO_RD_DATA_Pos 0UL
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#define I2S_RX_FIFO_RD_DATA_Msk 0xFFFFFFFFUL
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/* I2S.RX_FIFO_RD_SILENT */
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#define I2S_RX_FIFO_RD_SILENT_DATA_Pos 0UL
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#define I2S_RX_FIFO_RD_SILENT_DATA_Msk 0xFFFFFFFFUL
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/* I2S.INTR */
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#define I2S_INTR_TX_TRIGGER_Pos 0UL
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#define I2S_INTR_TX_TRIGGER_Msk 0x1UL
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#define I2S_INTR_TX_NOT_FULL_Pos 1UL
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#define I2S_INTR_TX_NOT_FULL_Msk 0x2UL
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#define I2S_INTR_TX_EMPTY_Pos 4UL
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#define I2S_INTR_TX_EMPTY_Msk 0x10UL
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#define I2S_INTR_TX_OVERFLOW_Pos 5UL
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#define I2S_INTR_TX_OVERFLOW_Msk 0x20UL
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#define I2S_INTR_TX_UNDERFLOW_Pos 6UL
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#define I2S_INTR_TX_UNDERFLOW_Msk 0x40UL
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#define I2S_INTR_TX_WD_Pos 8UL
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#define I2S_INTR_TX_WD_Msk 0x100UL
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#define I2S_INTR_RX_TRIGGER_Pos 16UL
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#define I2S_INTR_RX_TRIGGER_Msk 0x10000UL
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#define I2S_INTR_RX_NOT_EMPTY_Pos 18UL
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#define I2S_INTR_RX_NOT_EMPTY_Msk 0x40000UL
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#define I2S_INTR_RX_FULL_Pos 19UL
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#define I2S_INTR_RX_FULL_Msk 0x80000UL
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#define I2S_INTR_RX_OVERFLOW_Pos 21UL
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#define I2S_INTR_RX_OVERFLOW_Msk 0x200000UL
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#define I2S_INTR_RX_UNDERFLOW_Pos 22UL
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#define I2S_INTR_RX_UNDERFLOW_Msk 0x400000UL
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#define I2S_INTR_RX_WD_Pos 24UL
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#define I2S_INTR_RX_WD_Msk 0x1000000UL
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/* I2S.INTR_SET */
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#define I2S_INTR_SET_TX_TRIGGER_Pos 0UL
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#define I2S_INTR_SET_TX_TRIGGER_Msk 0x1UL
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#define I2S_INTR_SET_TX_NOT_FULL_Pos 1UL
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#define I2S_INTR_SET_TX_NOT_FULL_Msk 0x2UL
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#define I2S_INTR_SET_TX_EMPTY_Pos 4UL
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#define I2S_INTR_SET_TX_EMPTY_Msk 0x10UL
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#define I2S_INTR_SET_TX_OVERFLOW_Pos 5UL
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#define I2S_INTR_SET_TX_OVERFLOW_Msk 0x20UL
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#define I2S_INTR_SET_TX_UNDERFLOW_Pos 6UL
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#define I2S_INTR_SET_TX_UNDERFLOW_Msk 0x40UL
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#define I2S_INTR_SET_TX_WD_Pos 8UL
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#define I2S_INTR_SET_TX_WD_Msk 0x100UL
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#define I2S_INTR_SET_RX_TRIGGER_Pos 16UL
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#define I2S_INTR_SET_RX_TRIGGER_Msk 0x10000UL
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#define I2S_INTR_SET_RX_NOT_EMPTY_Pos 18UL
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#define I2S_INTR_SET_RX_NOT_EMPTY_Msk 0x40000UL
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#define I2S_INTR_SET_RX_FULL_Pos 19UL
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#define I2S_INTR_SET_RX_FULL_Msk 0x80000UL
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#define I2S_INTR_SET_RX_OVERFLOW_Pos 21UL
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#define I2S_INTR_SET_RX_OVERFLOW_Msk 0x200000UL
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#define I2S_INTR_SET_RX_UNDERFLOW_Pos 22UL
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#define I2S_INTR_SET_RX_UNDERFLOW_Msk 0x400000UL
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#define I2S_INTR_SET_RX_WD_Pos 24UL
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#define I2S_INTR_SET_RX_WD_Msk 0x1000000UL
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/* I2S.INTR_MASK */
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#define I2S_INTR_MASK_TX_TRIGGER_Pos 0UL
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#define I2S_INTR_MASK_TX_TRIGGER_Msk 0x1UL
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#define I2S_INTR_MASK_TX_NOT_FULL_Pos 1UL
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#define I2S_INTR_MASK_TX_NOT_FULL_Msk 0x2UL
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#define I2S_INTR_MASK_TX_EMPTY_Pos 4UL
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#define I2S_INTR_MASK_TX_EMPTY_Msk 0x10UL
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#define I2S_INTR_MASK_TX_OVERFLOW_Pos 5UL
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#define I2S_INTR_MASK_TX_OVERFLOW_Msk 0x20UL
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#define I2S_INTR_MASK_TX_UNDERFLOW_Pos 6UL
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#define I2S_INTR_MASK_TX_UNDERFLOW_Msk 0x40UL
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#define I2S_INTR_MASK_TX_WD_Pos 8UL
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#define I2S_INTR_MASK_TX_WD_Msk 0x100UL
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#define I2S_INTR_MASK_RX_TRIGGER_Pos 16UL
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#define I2S_INTR_MASK_RX_TRIGGER_Msk 0x10000UL
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#define I2S_INTR_MASK_RX_NOT_EMPTY_Pos 18UL
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#define I2S_INTR_MASK_RX_NOT_EMPTY_Msk 0x40000UL
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#define I2S_INTR_MASK_RX_FULL_Pos 19UL
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#define I2S_INTR_MASK_RX_FULL_Msk 0x80000UL
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#define I2S_INTR_MASK_RX_OVERFLOW_Pos 21UL
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#define I2S_INTR_MASK_RX_OVERFLOW_Msk 0x200000UL
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#define I2S_INTR_MASK_RX_UNDERFLOW_Pos 22UL
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#define I2S_INTR_MASK_RX_UNDERFLOW_Msk 0x400000UL
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#define I2S_INTR_MASK_RX_WD_Pos 24UL
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#define I2S_INTR_MASK_RX_WD_Msk 0x1000000UL
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/* I2S.INTR_MASKED */
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#define I2S_INTR_MASKED_TX_TRIGGER_Pos 0UL
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#define I2S_INTR_MASKED_TX_TRIGGER_Msk 0x1UL
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#define I2S_INTR_MASKED_TX_NOT_FULL_Pos 1UL
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#define I2S_INTR_MASKED_TX_NOT_FULL_Msk 0x2UL
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#define I2S_INTR_MASKED_TX_EMPTY_Pos 4UL
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#define I2S_INTR_MASKED_TX_EMPTY_Msk 0x10UL
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#define I2S_INTR_MASKED_TX_OVERFLOW_Pos 5UL
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#define I2S_INTR_MASKED_TX_OVERFLOW_Msk 0x20UL
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#define I2S_INTR_MASKED_TX_UNDERFLOW_Pos 6UL
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#define I2S_INTR_MASKED_TX_UNDERFLOW_Msk 0x40UL
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#define I2S_INTR_MASKED_TX_WD_Pos 8UL
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#define I2S_INTR_MASKED_TX_WD_Msk 0x100UL
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#define I2S_INTR_MASKED_RX_TRIGGER_Pos 16UL
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#define I2S_INTR_MASKED_RX_TRIGGER_Msk 0x10000UL
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#define I2S_INTR_MASKED_RX_NOT_EMPTY_Pos 18UL
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#define I2S_INTR_MASKED_RX_NOT_EMPTY_Msk 0x40000UL
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#define I2S_INTR_MASKED_RX_FULL_Pos 19UL
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#define I2S_INTR_MASKED_RX_FULL_Msk 0x80000UL
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#define I2S_INTR_MASKED_RX_OVERFLOW_Pos 21UL
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#define I2S_INTR_MASKED_RX_OVERFLOW_Msk 0x200000UL
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#define I2S_INTR_MASKED_RX_UNDERFLOW_Pos 22UL
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#define I2S_INTR_MASKED_RX_UNDERFLOW_Msk 0x400000UL
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#define I2S_INTR_MASKED_RX_WD_Pos 24UL
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#define I2S_INTR_MASKED_RX_WD_Msk 0x1000000UL
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#endif /* _CYIP_I2S_H_ */
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/* [] END OF FILE */
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