mirror of https://github.com/ARMmbed/mbed-os.git
129 lines
3.5 KiB
C
129 lines
3.5 KiB
C
/* mbed Microcontroller Library
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* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "sleep_api.h"
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// Number of warm-up cycle in EHOSC = (warming up time (s) / clock period (s)) - 16
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#define CG_WUODR_EXT_5MS ((uint16_t)0xC340)
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// Number of warm-up cycle in IHOSC = ((warming up time (s) – 63.3(μs) / clock period (s)) - 41
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#define CG_WUODR_INT_67_4us ((uint16_t)0x0000)
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#define CG_STBY_MODE_IDLE 0x0
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#define CG_STBY_MODE_STOP1 0x1
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#define EXTERNEL_OSC_MASK 0xFFFFFFF1
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#define SIWDT_DISABLE 0xB1
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#define WUPT_LOWER_MASK 0x000F
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#define WUPT_UPPER_MASK 0xFFF0
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static void external_hosc_enable(void);
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void hal_sleep(void)
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{
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// Set low power consumption mode IDLE
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TSB_CG->STBYCR = CG_STBY_MODE_IDLE;
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// Enter idle mode
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__DSB();
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__WFI();
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}
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void hal_deepsleep(void)
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{
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uint32_t wupt_lower = 0;
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uint32_t wupt_upper = 0;
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uint32_t tmp = 0;
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TSB_CG_FSYSMENB_IPMENB31 = TXZ_ENABLE;
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TSB_SIWD0->EN = TXZ_DISABLE;
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TSB_SIWD0->CR = SIWDT_DISABLE;
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while ((TSB_FC->SR0 & TXZ_DONE) != TXZ_DONE) {
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// Flash wait
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}
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while (TSB_CG_WUPHCR_WUEF) {
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// Wait for end of Warming-up for IHOSC1
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}
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TSB_CG_WUPHCR_WUCLK = TXZ_DISABLE;
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wupt_lower = ((CG_WUODR_INT_67_4us & WUPT_LOWER_MASK) << 16U);
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wupt_upper = ((CG_WUODR_INT_67_4us & WUPT_UPPER_MASK) << 16U);
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TSB_CG->WUPHCR |= (wupt_lower | wupt_upper);
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TSB_CG->STBYCR = CG_STBY_MODE_STOP1;
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TSB_CG_PLL0SEL_PLL0SEL = TXZ_DISABLE;
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while (TSB_CG_PLL0SEL_PLL0ST) {
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// Wait for PLL status of fsys until off state(fosc=0)
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}
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// Stop PLL of fsys
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TSB_CG_PLL0SEL_PLL0ON = TXZ_DISABLE;
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TSB_CG_OSCCR_IHOSC1EN = TXZ_ENABLE;
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TSB_CG_OSCCR_OSCSEL = TXZ_DISABLE;
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while (TSB_CG_OSCCR_OSCF) {
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// Wait for fosc status until IHOSC1 = 0
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}
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tmp = TSB_CG->OSCCR;
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tmp &= EXTERNEL_OSC_MASK;
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TSB_CG->OSCCR = tmp;
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// Enter stop1 mode
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__DSB();
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__WFI();
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// Switch over from IHOSC to EHOSC
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// After coming out off sleep mode, Restore the clock setting to EHOSC.
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external_hosc_enable();
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}
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static void external_hosc_enable(void)
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{
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uint32_t wupt_lower = 0;
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uint32_t wupt_upper = 0;
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// Enable high-speed oscillator
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TSB_CG->OSCCR |= (TXZ_ENABLE << 1);
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// Select internal(fIHOSC) as warm-up clock
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wupt_lower = ((CG_WUODR_EXT_5MS & WUPT_LOWER_MASK) << 16U);
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wupt_upper = ((CG_WUODR_EXT_5MS & WUPT_UPPER_MASK) << 16U);
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TSB_CG->WUPHCR |= (wupt_lower | wupt_upper);
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// Start warm-up
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TSB_CG->WUPHCR |= TXZ_ENABLE;
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// Wait until EHOSC become stable
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while ((TSB_CG->WUPHCR & 0x0002)) {
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// Do nothing
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}
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// Set fosc source
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TSB_CG->OSCCR |= (1 << 8);
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// Wait for <OSCSEL> to become "1"
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while (!((TSB_CG->OSCCR & 0x200) >> 9)) {
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// Do nothing
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}
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// Stop IHOSC
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TSB_CG->OSCCR &= ~TXZ_ENABLE;
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}
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