mirror of https://github.com/ARMmbed/mbed-os.git
531 lines
23 KiB
C
531 lines
23 KiB
C
/**
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*******************************************************************************
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* @file system_TMPM4KyA.c
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* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for the
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* TOSHIBA 'TMPM4Ky' Device Series
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* @version V1.0.0
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*
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* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
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*
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* Copyright(C) Toshiba Electronic Device Solutions Corporation 2022
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*******************************************************************************
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*/
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#include "TMPM4KNA.h"
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/*-------- <<< Start of configuration section >>> ----------------------------*/
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#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */
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#define FC_ACCR_FDLC_4 (0x00000300UL) /*!< Data Flash read clock 4clock */
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#define FC_ACCR_FDLC_5 (0x00000400UL) /*!< Data Flash read clock 5clock */
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#define FC_ACCR_FDLC_6 (0x00000500UL) /*!< Data Flash read clock 6clock */
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#define FC_ACCR_FCLC_1 (0x00000000UL) /*!< Code Flash read clock 1clock */
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#define FC_ACCR_FCLC_2 (0x00000001UL) /*!< Code Flash read clock 2clock */
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#define FC_ACCR_FCLC_3 (0x00000002UL) /*!< Code Flash read clock 3clock */
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#define FC_ACCR_FCLC_4 (0x00000003UL) /*!< Code Flash read clock 4clock */
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#define FC_ACCR_FCLC_5 (0x00000004UL) /*!< Code Flash read clock 5clock */
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#define FC_ACCR_FCLC_6 (0x00000005UL) /*!< Code Flash read clock 6clock */
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#define SYSCORECLOCK_80M (80000000UL) /*!< 80MHz */
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/* Clock Generator (CG) Configuration */
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#define CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */
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#define CG_GEAR_FC_1 (0x00000000UL) /*!< CG fc register value */
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#define CG_GEAR_FC_2 (0x00000001UL) /*!< CG fc/2 register value */
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#define CG_GEAR_FC_4 (0x00000002UL) /*!< CG fc/4 register value */
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#define CG_GEAR_FC_8 (0x00000003UL) /*!< CG fc/8 register value */
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#define CG_GEAR_FC_16 (0x00000004UL) /*!< CG fc/16 register value */
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#define CG_PRCK_FC_1 (0x00000000UL) /*!< CG PhiT0 fc register value */
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#define CG_PRCK_FC_2 (0x00000100UL) /*!< CG PhiT0 fc/2 register value */
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#define CG_PRCK_FC_4 (0x00000200UL) /*!< CG PhiT0 fc/4 register value */
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#define CG_PRCK_FC_8 (0x00000300UL) /*!< CG PhiT0 fc/8 register value */
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#define CG_PRCK_FC_16 (0x00000400UL) /*!< CG PhiT0 fc/16 register value */
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#define CG_PRCK_FC_32 (0x00000500UL) /*!< CG PhiT0 fc/32 register value */
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#define CG_PRCK_FC_64 (0x00000600UL) /*!< CG PhiT0 fc/64 register value */
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#define CG_PRCK_FC_128 (0x00000700UL) /*!< CG PhiT0 fc/128 register value*/
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#define CG_PRCK_FC_256 (0x00000800UL) /*!< CG PhiT0 fc/256 register value*/
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#define CG_PRCK_FC_512 (0x00000900UL) /*!< CG PhiT0 fc/512 register value*/
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#define CG_MCKSEL_1 (0x00000000UL) /*!< CG fsysm, mPhiT0 fc value */
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#define CG_MCKSEL_2 (0x00000040UL) /*!< CG fsysm, mPhiT0 fc/2 value */
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#define CG_MCKSEL_4 (0x00000080UL) /*!< CG fsysm, mPhiT0 fc/4 value */
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#define CG_GEAR_MASK ((uint32_t)0x00000007) /*!< CG GEAR mask */
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#define CG_PRCK_MASK ((uint32_t)0x00000F00) /*!< CG PRCK mask */
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#define CG_MCKSEL_MASK ((uint32_t)0x000000C0) /*!< CG MCKSEL mask */
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#define CG_PRCKST_MASK ((uint32_t)0x0F000000) /*!< CG PRCKST mask */
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#define CG_MCKSELPST_MASK ((uint32_t)0xC0000000) /*!< CG MCKSELPST mask */
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#define CG_MCKSELGST_MASK ((uint32_t)0x00C00000) /*!< CG MCKSELGST mask */
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#define SYSCR_Val (CG_GEAR_FC_1 | CG_PRCK_FC_1 | CG_MCKSEL_2)
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#define STBYCR_Val (0x00000000UL)
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/* Define clocks */
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#define IOSC_10M_DIV2_PLLON (160000000UL) /* 10.00MHz * 32.0000 / 2 */
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#define EOSC_6M (6000000UL)
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#define EOSC_8M (8000000UL)
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#define EOSC_10M (10000000UL)
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#define EOSC_12M (12000000UL)
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#define EXTALH EOSC_10M /* External high-speed oscillator freq */
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#define EOSC_6M_DIV2_PLLON (159900000UL) /* 6.00MHz * 53.3125 / 2 */
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#define EOSC_8M_DIV2_PLLON (160000000UL) /* 8.00MHz * 40.0000 / 2 */
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#define EOSC_10M_DIV2_PLLON (160000000UL) /* 10.00MHz * 32.0000 / 2 */
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#define EOSC_12M_DIV2_PLLON (159800000UL) /* 12.00MHz * 26.6250 / 2 */
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#define FIXED_6MHz (6000000UL) /* 6.00MHz */
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#define FIXED_8MHz (8000000UL) /* 8.00MHz */
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#define FIXED_10MHz (10000000UL) /* 10.00MHz */
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#define FIXED_12MHz (12000000UL) /* 12.00MHz */
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#define FIXED_160MHz (160000000UL)
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#define IOSC_10M (10000000UL)
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#define IXTALH IOSC_10M /* Internal high-speed oscillator freq */
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#define CG_6M_MUL_26_656_FPLL (0x001C1535UL<<8U) /* fPLL = 6MHz * 26.656 */
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#define CG_8M_MUL_20_FPLL (0x00245028UL<<8U) /* fPLL = 8MHz * 20 */
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#define CG_10M_MUL_16_FPLL (0x002E9020UL<<8U) /* fPLL = 10MHz * 16 */
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#define CG_12M_MUL_13_312_FPLL (0x0036DA1AUL<<8U) /* fPLL = 12MHz * 13.312 */
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#define CG_PLL0SEL_FPLL ((uint32_t)0x00000002) /*!< CG PLL0SEL fPLL */
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#define CG_PLL0SEL_FOSC ((uint32_t)0x00000000) /*!< CG PLL0SEL fosc */
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#define PLL0SEL_MASK (0xFFFFFF00UL) /*!< CG PLL mask */
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#define CG_PLL0SEL_PLL0ON_SET ((uint32_t)0x00000001)
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#define CG_PLL0SEL_PLL0ON_CLEAR ((uint32_t)0xFFFFFFFE)
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#define CG_PLL0SEL_PLL0SEL_SET ((uint32_t)0x00000002)
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#define CG_PLL0SEL_PLL0SEL_CLEAR ((uint32_t)0xFFFFFFFD)
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#define CG_OSCSEL_EHOSC ((uint32_t)0x00000100) /*!< CG OSCSEL EHOSC */
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#define CG_OSCCR_IHOSC1EN_CLEAR ((uint32_t)0xFFFFFFFE)
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#define CG_OSCCR_EOSCEN_SET ((uint32_t)0x00000002)
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#define CG_OSCCR_OSCSEL_SET ((uint32_t)0x00000100)
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/* Configure Warm-up time */
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#define HZ_1M (1000000UL)
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#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */
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#define WU_TIME_INT (1634UL) /* warm-up time for INT is 163.4us x 10 */
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#define WU_TIME_INT_MIN (0x03C << 20U) /* minimum warm-up time for INT */
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#define CGWUPHCR_WUEF_R_DONE ((uint32_t)0x00000000) /*!< WUEF :[R] :Done */
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/* Warm-up setting value */
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/* EOSC OSCCR<WUPT11:0> = (warm-up time(us) * EXTALH - 16) / 16 */
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#define WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * EXTALH / HZ_1M) - 16UL) /16UL) << 20U))
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/* IOSC OSCCR<WUPT11:0> = ((warm-up time(us) - 63.3us) * IXTALH - 41) / 16 */
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#define WUPHCR_WUPT_INT ((uint32_t)(((((uint64_t)(WU_TIME_INT - 633UL) * (IXTALH / 10) / HZ_1M) - 41UL) / 16UL) << 20U))
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#define CG_WUPHCR_WUON_START_SET ((uint32_t)0x00000001)
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#if (CLOCK_SETUP)
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#define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000100)
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#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U))
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#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U))
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#define PLL0SEL_Ready CG_10M_MUL_16_FPLL
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#else
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#define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000000)
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#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)((INIT_TIME_PLL * 10) - 633UL) * (IXTALH / 10) / HZ_1M) - 41UL) /16UL) << 20U))
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#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)((LOCKUP_TIME_PLL * 10) - 633UL) * (IXTALH /10) / HZ_1M) - 41UL) /16UL) << 20U))
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#define PLL0SEL_Ready CG_10M_MUL_12_FPLL
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#endif
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/* Semi-Independent Watchdog Timer (SIWDT) Configuration */
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#define SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */
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#define SIWDEN_Val (0x00000000UL) /* SIWD Disable */
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#define SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */
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#define PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL)
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#if defined ( __CC_ARM ) || defined(__ARMCC_VERSION) /* RealView Compiler */
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extern uint32_t Load$$FLASH_CODE_RAM$$Base;
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extern uint32_t Image$$FLASH_CODE_RAM$$Base;
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extern uint32_t Load$$FLASH_CODE_RAM$$Length;
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#elif defined ( __ICCARM__ ) /* IAR Compiler */
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#pragma section = "FLASH_CODE_RAM"
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#pragma section = "FLASH_CODE_ROM"
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#endif
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#if defined ( __CC_ARM ) || defined(__ARMCC_VERSION) /* RealView Compiler */
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#define FLASH_API_ROM (uint32_t *)&Load$$FLASH_CODE_RAM$$Base
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#define FLASH_API_RAM (uint32_t *)&Image$$FLASH_CODE_RAM$$Base
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#define SIZE_FLASH_API (uint32_t)&Load$$FLASH_CODE_RAM$$Length
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#elif defined ( __ICCARM__ ) /* IAR Compiler */
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#define FLASH_API_ROM ((uint32_t *)__section_begin("FLASH_CODE_ROM"))
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#define FLASH_API_RAM ((uint32_t *)__section_begin("FLASH_CODE_RAM"))
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#define SIZE_FLASH_API ((uint32_t)__section_size("FLASH_CODE_ROM"))
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#endif
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/*-------- <<< End of configuration section >>> ------------------------------*/
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/*-------- DEFINES -----------------------------------------------------------*/
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/* Configure Warm-up time */
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#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */
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#define INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */
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#define LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */
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/* Determine core clock frequency according to settings */
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/* System clock is high-speed clock*/
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#if (CLOCK_SETUP)
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#define CORE_TALH (EXTALH)
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#else
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#define CORE_TALH (IXTALH)
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#endif
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#if ((PLL0SEL_Val & (1U<<1U)) && (PLL0SEL_Val & (1U<<0U))) /* If PLL selected and enabled */
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#if (CORE_TALH == EOSC_6M) /* If input is 6MHz */
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#if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_6M_MUL_26_656_FPLL))
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#define __CORE_CLK EOSC_6M_DIV2_PLLON /* output clock is 159.938MHz */
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#else /* fc -> reserved */
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#define __CORE_CLK (0U)
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#endif /* End input is 6MHz */
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#elif (CORE_TALH == EOSC_8M) /* If input is 8MHz */
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#if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_20_FPLL))
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#define __CORE_CLK EOSC_8M_DIV2_PLLON /* output clock is 160MHz */
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#else /* fc -> reserved */
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#define __CORE_CLK (0U)
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#endif /* End input is 8MHz */
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#elif (CORE_TALH == EOSC_10M) /* If input is 10MHz */
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#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL)
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#define __CORE_CLK EOSC_10M_DIV2_PLLON /* output clock is 160MHz */
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#else /* fc -> reserved */
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#define __CORE_CLK (0U)
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#endif /* End input is 10MHz */
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#elif (CORE_TALH == EOSC_12M) /* If input is 12MHz */
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#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_13_312_FPLL)
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#define __CORE_CLK EOSC_12M_DIV2_PLLON /* output clock is 159.75MHz */
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#else /* fc -> reserved */
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#define __CORE_CLK (0U)
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#endif /* End input is 12MHz */
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#elif (CORE_TALH == IOSC_10M) /* If input is 10MHz */
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#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL)
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#define __CORE_CLK IOSC_10M_DIV2_PLLON /* output clock is 160MHz */
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#else /* fc -> reserved */
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#define __CORE_CLK (0U)
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#endif /* End input is 12MHz */
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#else /* input clock not known */
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#define __CORE_CLK (0U)
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#error "Core Oscillator Frequency invalid!"
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#endif /* End switch input clock */
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#else /* If PLL not used */
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#define __CORE_CLK (CORE_TALH)
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#endif
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#if ((SYSCR_Val & 7U) == 0U) /* Gear -> fc */
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#define __CORE_SYS (__CORE_CLK)
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#elif ((SYSCR_Val & 7U) == 1U) /* Gear -> fc/2 */
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#define __CORE_SYS (__CORE_CLK / 2U)
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#elif ((SYSCR_Val & 7U) == 2U) /* Gear -> fc/4 */
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#define __CORE_SYS (__CORE_CLK / 4U )
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#elif ((SYSCR_Val & 7U) == 3U) /* Gear -> fc/8 */
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#define __CORE_SYS (__CORE_CLK / 8U)
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#elif ((SYSCR_Val & 7U) == 4U) /* Gear -> fc/16 */
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#define __CORE_SYS (__CORE_CLK / 16U)
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#else /* Gear -> reserved */
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#define __CORE_SYS (0U)
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#endif
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/* Clock Variable definitions */
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uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */
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/**
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* Initialize the system
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*
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* @param none
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* @return none
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*
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* @brief Update SystemCoreClock according register values.
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*/
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void SystemCoreClockUpdate(void)
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{
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/* Get Core Clock Frequency */
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uint32_t CoreClock = 0U;
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uint32_t CoreClockInput = 0U;
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uint32_t regval = 0U;
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uint32_t oscsel = 0U;
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uint32_t pll0sel = 0U;
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uint32_t pll0on = 0U;
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/* Determine clock frequency according to clock register values */
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/* System clock is high-speed clock */
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regval = TSB_CG->OSCCR;
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oscsel = regval & CG_OSCSEL_EHOSC;
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if (oscsel) { /* If system clock is External high-speed oscillator freq */
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CoreClock = EXTALH;
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} else { /* If system clock is Internal high-speed oscillator freq */
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CoreClock = IXTALH;
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}
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regval = TSB_CG->PLL0SEL;
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pll0sel = regval & CG_PLL0SEL_FPLL;
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pll0on = regval & CG_PLL0SEL_PLL0ON_SET;
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if (pll0sel && pll0on) { /* If PLL enabled */
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if (CoreClock == EOSC_6M) { /* If input is 6MHz */
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if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_6M_MUL_26_656_FPLL) {
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CoreClockInput = EOSC_6M_DIV2_PLLON; /* output clock is 159.938MHz */
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} else {
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CoreClockInput = 0U; /* fc -> reserved */
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}
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} else if (CoreClock == EOSC_8M) { /* If input is 8MHz */
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if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_20_FPLL) {
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CoreClockInput = EOSC_8M_DIV2_PLLON; /* output clock is 160MHz */
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} else {
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CoreClockInput = 0U; /* fc -> reserved */
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}
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} else if (CoreClock == EOSC_10M) { /* If input is 10MHz */
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if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL) {
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CoreClockInput = EOSC_10M_DIV2_PLLON; /* output clock is 160MHz */
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} else {
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CoreClockInput = 0U; /* fc -> reserved */
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}
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} else if (CoreClock == EOSC_12M) { /* If input is 12MHz */
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if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_13_312_FPLL) {
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CoreClockInput = EOSC_12M_DIV2_PLLON; /* output clock is 159.75MHz */
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} else {
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CoreClockInput = 0U; /* fc -> reserved */
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}
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} else if (CoreClock == IOSC_10M) { /* If input is 10MHz */
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if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL) {
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CoreClockInput = EOSC_10M_DIV2_PLLON; /* output clock is 160MHz */
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} else {
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CoreClockInput = 0U; /* fc -> reserved */
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}
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} else {
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CoreClockInput = 0U;
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}
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} else { /* If PLL not used */
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CoreClockInput = CoreClock;
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}
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switch (TSB_CG->SYSCR & 7U) {
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case 0U: /* Gear -> fc */
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SystemCoreClock = CoreClockInput;
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break;
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case 1U: /* Gear -> fc/2 */
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SystemCoreClock = CoreClockInput / 2U;
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break;
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case 2U: /* Gear -> fc/4 */
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SystemCoreClock = CoreClockInput / 4U;
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break;
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case 3U: /* Gear -> fc/8 */
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if (CoreClockInput >= EOSC_8M) {
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SystemCoreClock = CoreClockInput / 8U;
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} else {
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SystemCoreClock = 0U;
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}
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break;
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case 4U: /* Gear -> fc/16 */
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if (CoreClockInput > EOSC_12M) {
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SystemCoreClock = CoreClockInput / 16U;
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} else {
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SystemCoreClock = 0U;
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}
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break;
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case 5U:
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case 6U:
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case 7U:
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SystemCoreClock = 0U;
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break;
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default:
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SystemCoreClock = 0U;
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break;
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}
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}
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#if defined ( __CC_ARM ) || defined ( __ICCARM__ ) || defined(__ARMCC_VERSION)
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static void CopyRoutine(uint32_t *dest, uint32_t *source, uint32_t size);
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#endif
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static void FlashReadClockSet(uint32_t sysclock);
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/*--------------------------------------------------*/
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/**
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* @brief copy 32-bit data from source to dest
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* @param the address of source and dast, the data size
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* @retval none.
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* @note -
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*/
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/*--------------------------------------------------*/
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static void CopyRoutine(uint32_t *dest, uint32_t *source, uint32_t size)
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{
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uint32_t *dest_addr, *source_addr, tmpsize;
|
|
uint32_t i, tmps, tmpd, mask;
|
|
|
|
dest_addr = dest;
|
|
source_addr = source;
|
|
|
|
tmpsize = size >> 2U;
|
|
for (i = 0U; i < tmpsize; i++) { /* 32bits copy */
|
|
*dest_addr = *source_addr;
|
|
dest_addr++;
|
|
source_addr++;
|
|
}
|
|
if (size & 0x00000003U) { /* if the last data size is not 0(maybe 1,2 or 3), copy the last data */
|
|
mask = 0xFFFFFF00U;
|
|
i = size & 0x00000003U;
|
|
tmps = *source_addr;
|
|
tmpd = *dest_addr;
|
|
while (i - 1U) {
|
|
mask = mask << 8U;
|
|
i--;
|
|
}
|
|
tmps = tmps & (~mask);
|
|
tmpd = tmpd & (mask);
|
|
*dest_addr = tmps + tmpd; /* 32bits copy, but only change the bytes need to be changed */
|
|
} else {
|
|
/* Do nothing */
|
|
}
|
|
}
|
|
|
|
|
|
/**
|
|
* Initialize the system
|
|
*
|
|
* @param none
|
|
* @return none
|
|
*
|
|
* @brief Setup the microcontroller system.
|
|
* Initialize the System.
|
|
*/
|
|
void SystemInit(void)
|
|
{
|
|
#if (SIWD_SETUP) /* Watchdog Setup */
|
|
/* SIWD Disable */
|
|
TSB_SIWD0->EN = SIWDEN_Val;
|
|
TSB_SIWD0->CR = SIWDCR_Val;
|
|
#else
|
|
/* SIWD Enable (Setting after a Reset) */
|
|
#endif
|
|
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) /* FPU setting */
|
|
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
|
|
#endif
|
|
|
|
#if defined ( __CC_ARM ) || defined ( __ICCARM__ ) || defined(__ARMCC_VERSION)
|
|
CopyRoutine(FLASH_API_RAM, FLASH_API_ROM, SIZE_FLASH_API); /* copy flash API to RAM */
|
|
#endif
|
|
FlashReadClockSet(FIXED_160MHz);
|
|
|
|
#if (CLOCK_SETUP) /* Clock(external) Setup */
|
|
|
|
TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET;
|
|
TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET);
|
|
TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
|
|
while (TSB_CG_WUPHCR_WUEF) {
|
|
;
|
|
} /* Warm-up */
|
|
TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET;
|
|
while (!TSB_CG_OSCCR_OSCF) {
|
|
;
|
|
} /* Confirm CGOSCCR<OSCF>="1" */
|
|
#else
|
|
/* Internal HOSC Enable (Setting after a Reset) */
|
|
#endif
|
|
|
|
TSB_CG->SYSCR = SYSCR_Val;
|
|
while ((TSB_CG->SYSCR & CG_MCKSELGST_MASK) != ((SYSCR_Val & CG_MCKSEL_MASK) << 16U)) {
|
|
;
|
|
} /* Confirm CGSYSCCR<MCKSELGST>="01" */
|
|
while ((TSB_CG->SYSCR & CG_MCKSELPST_MASK) != ((SYSCR_Val & CG_MCKSEL_MASK) << 24U)) {
|
|
;
|
|
} /* Confirm CGSYSCR<MCKSELPST>="01" */
|
|
while ((TSB_CG->SYSCR & CG_PRCKST_MASK) != ((SYSCR_Val & CG_PRCK_MASK) << 16U)) {
|
|
;
|
|
} /* Confirm CGSYSCR<PRCKST>="0000" */
|
|
|
|
#if (CLOCK_SETUP) /* Clock(external) Setup */
|
|
TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET);
|
|
#else
|
|
TSB_CG->WUPHCR = (WUPHCR_INIT_PLL);
|
|
#endif
|
|
TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0SEL_CLEAR; /* PLL-->fOsc */
|
|
TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR;
|
|
TSB_CG->PLL0SEL = PLL0SEL_Ready;
|
|
#if (CLOCK_SETUP) /* Clock(external) Setup */
|
|
TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
|
|
#else
|
|
TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUON_START_SET);
|
|
#endif
|
|
|
|
while (TSB_CG_WUPHCR_WUEF) {
|
|
;
|
|
} /* Warm-up */
|
|
|
|
#if (CLOCK_SETUP) /* Clock(external) Setup */
|
|
TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET);
|
|
#else
|
|
TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL);
|
|
#endif
|
|
TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */
|
|
TSB_CG->STBYCR = STBYCR_Val;
|
|
|
|
#if (CLOCK_SETUP) /* Clock(external) Setup */
|
|
TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
|
|
#else
|
|
TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUON_START_SET);
|
|
#endif
|
|
while (TSB_CG_WUPHCR_WUEF) {
|
|
;
|
|
} /* Warm-up */
|
|
|
|
TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET;
|
|
while (!TSB_CG_PLL0SEL_PLL0ST) {
|
|
;
|
|
} /*Confirm CGPLL0SEL<PLL0ST> = "1" */
|
|
|
|
#if (CLOCK_SETUP) /* Clock(external) Setup */
|
|
TSB_CG->OSCCR &= CG_OSCCR_IHOSC1EN_CLEAR;
|
|
#endif
|
|
}
|
|
|
|
/*--------------------------------------------------*/
|
|
/**
|
|
* @brief Raed clock set.
|
|
* @param none.
|
|
* @retval none.
|
|
* @note It works in the inner RAM.
|
|
*/
|
|
/*--------------------------------------------------*/
|
|
#if defined ( __CC_ARM ) /* RealView Compiler */
|
|
#pragma arm section code="FLASH_ROM"
|
|
#elif defined ( __ICCARM__ ) /* IAR Compiler */
|
|
#pragma location = "FLASH_ROM"
|
|
#elif defined(__ARMCC_VERSION)
|
|
__attribute__((section("FLASH_ROM")))
|
|
#else /* GCC Compiler */
|
|
__attribute__((section(".ram_func")))
|
|
#endif
|
|
static void FlashReadClockSet(uint32_t sysclock)
|
|
{
|
|
uint32_t regval = 0;
|
|
|
|
if (sysclock > SYSCORECLOCK_80M) {
|
|
regval = (uint32_t)(FC_ACCR_FDLC_5 | FC_ACCR_FCLC_5);
|
|
TSB_FC->KCR = FC_KCR_KEYCODE;
|
|
TSB_FC->FCACCR = regval;
|
|
while (TSB_FC->FCACCR != (uint32_t)(FC_ACCR_FDLC_5 | FC_ACCR_FCLC_5)) {
|
|
/* no processing */
|
|
}
|
|
} else {
|
|
regval = (uint32_t)(FC_ACCR_FDLC_4 | FC_ACCR_FCLC_4);
|
|
TSB_FC->KCR = FC_KCR_KEYCODE;
|
|
TSB_FC->FCACCR = regval;
|
|
while (TSB_FC->FCACCR != (uint32_t)(FC_ACCR_FDLC_4 | FC_ACCR_FCLC_4)) {
|
|
/* no processing */
|
|
}
|
|
}
|
|
}
|