mirror of https://github.com/ARMmbed/mbed-os.git
120 lines
4.4 KiB
C
120 lines
4.4 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2019 ARM Limited
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* Copyright (c) 2019 STMicroelectronics
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* This file configures the system clock as follows:
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*-----------------------------------------------------------------------------
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* System clock source | HSE (external 32 MHz clock)
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*-----------------------------------------------------------------------------
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* SYSCLK(MHz) | 32
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* AHBCLK (MHz) | 32
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* APB1CLK (MHz) | 32
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* APB2CLK (MHz) | 32
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* USB capable | YES
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*-----------------------------------------------------------------------------
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**/
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#include "stm32wbxx.h"
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#include "mbed_error.h"
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#include "stm32wbxx_ll_hsem.h"
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#include "otp.h"
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static void Config_HSE(void)
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{
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OTP_ID0_t *p_otp;
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/**
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* Read HSE_Tuning from OTP
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*/
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p_otp = (OTP_ID0_t *) OTP_Read(0);
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if (p_otp) {
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LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
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}
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return;
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}
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/**
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* @brief Configures the System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers
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* @note This function should be called only once the RCC clock configuration
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* is reset to the default reset state (done in SystemInit() function).
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* @param None
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* @retval None
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*/
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void SetSysClock(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
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__HAL_RCC_HSEM_CLK_ENABLE();
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/* This prevents the CPU2 (M0+) to configure RCC */
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while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID));
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Config_HSE();
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/* Initializes the CPU, AHB and APB busses clocks */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.LSEState = RCC_LSE_ON;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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error("HAL_RCC_OscConfig error\n");
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}
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/** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers */
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_HCLK2
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| RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
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error("HAL_RCC_ClockConfig error\n");
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}
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/* Initializes the peripherals clocks */
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/* RNG needs to be configured like in M0 core, i.e. with HSI48 */
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_RFWAKEUP | RCC_PERIPHCLK_RNG ;
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PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_LSE;
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PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
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PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
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PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
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error("HAL_RCCEx_PeriphCLKConfig error\n");
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}
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LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
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LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
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// LL_PWR_SMPS_Enable();
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/* Select HSI as system clock source after Wake Up from Stop mode */
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LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
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LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, 0);
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}
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