mirror of https://github.com/ARMmbed/mbed-os.git
108 lines
3.4 KiB
C
108 lines
3.4 KiB
C
/*
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* Copyright (c) 2015-2016, Nuvoton Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "analogin_api.h"
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void mbed_sdk_init(void)
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{
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// NOTE: Support singleton semantics to be called from other init functions
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static int inited = 0;
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if (inited) {
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return;
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}
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inited = 1;
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/*---------------------------------------------------------------------------------------------------------*/
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/* Init System Clock */
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/*---------------------------------------------------------------------------------------------------------*/
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/* Unlock protected registers */
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SYS_UnlockReg();
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/* Enable HIRC clock (Internal RC 22.1184MHz) */
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CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
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#if MBED_CONF_TARGET_HXT_PRESENT
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/* Enable HXT clock (external XTAL 12MHz) */
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CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
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#else
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/* Disable HXT clock (external XTAL 12MHz) */
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CLK_DisableXtalRC(CLK_PWRCTL_HXTEN_Msk);
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#endif
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/* Enable LIRC */
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CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
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#if MBED_CONF_TARGET_LXT_PRESENT
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/* Enable LXT */
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CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
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#else
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/* Disable LXT */
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CLK_DisableXtalRC(CLK_PWRCTL_LXTEN_Msk);
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#endif
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/* Wait for HIRC clock ready */
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CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
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#if MBED_CONF_TARGET_HXT_PRESENT
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/* Wait for HXT clock ready */
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CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
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#endif
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/* Wait for LIRC clock ready */
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CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
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#if MBED_CONF_TARGET_LXT_PRESENT
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/* Wait for LXT clock ready */
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CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
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#endif
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/* Select HCLK clock source as HIRC and HCLK clock divider as 1 */
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CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
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/* Set core clock as 192000000 from PLL */
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CLK_SetCoreClock(192000000);
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/* Set PCLK0/PCLK1 to HCLK/2 */
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CLK->PCLKDIV = (CLK_PCLKDIV_PCLK0DIV2 | CLK_PCLKDIV_PCLK1DIV2); // PCLK divider set 2
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#if DEVICE_ANALOGIN
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/* Vref connect to internal */
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SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_3_0V;
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#endif
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/* Update System Core Clock */
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/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
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SystemCoreClockUpdate();
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/* Lock protected registers */
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SYS_LockReg();
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/* Get around h/w limit with WDT reset from PD */
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if (SYS_IS_WDT_RST()) {
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/* Re-unlock protected clock setting */
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SYS_UnlockReg();
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/* Set up DPD power down mode */
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CLK->PMUSTS |= CLK_PMUSTS_CLRWK_Msk;
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CLK->PMUSTS |= CLK_PMUSTS_TMRWK_Msk;
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CLK_SetPowerDownMode(CLK_PMUCTL_PDMSEL_DPD);
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CLK_SET_WKTMR_INTERVAL(CLK_PMUCTL_WKTMRIS_256);
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CLK_ENABLE_WKTMR();
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CLK_PowerDown();
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/* Lock protected registers */
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SYS_LockReg();
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}
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}
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