mirror of https://github.com/ARMmbed/mbed-os.git
127 lines
4.6 KiB
C
127 lines
4.6 KiB
C
/**************************************************************************//**
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* @file system_M480.c
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* @version V1.000
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* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M480
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#include "NuMicro.h"
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/*----------------------------------------------------------------------------
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DEFINES
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*----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------
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Clock Variable definitions
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*----------------------------------------------------------------------------*/
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uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
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uint32_t CyclesPerUs = (__HSI / 1000000UL); /* Cycles per micro second */
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uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
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uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0UL, __LIRC, 0UL, 0UL, 0UL, __HIRC};
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/*----------------------------------------------------------------------------
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Clock functions
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*----------------------------------------------------------------------------*/
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void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
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{
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uint32_t u32Freq, u32ClkSrc;
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uint32_t u32HclkDiv;
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/* Update PLL Clock */
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PllClock = CLK_GetPLLClockFreq();
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u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
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if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL)
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{
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/* Use PLL clock */
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u32Freq = PllClock;
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}
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else
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{
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/* Use the clock sources directly */
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u32Freq = gau32ClkSrcTbl[u32ClkSrc];
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}
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u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL;
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/* Update System Core Clock */
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SystemCoreClock = u32Freq / u32HclkDiv;
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//if(SystemCoreClock == 0)
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// __BKPT(0);
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CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL;
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}
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#if MBED_CONF_TARGET_HXT_PRESENT
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/**
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* @brief Set PF.2 and PF.3 to input mode
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* @param None
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* @return None
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* @details GPIO default state could be configured as input or quasi through user config.
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* To use HXT, PF.2 and PF.3 must not set as quasi mode. This function changes
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* PF.2 and PF.3 to input mode no matter which mode they are working at.
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*/
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static __INLINE void HXTInit(void)
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{
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PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);
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}
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#endif
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/**
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* @brief Initialize the System
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*
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* @param none
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* @return none
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*/
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void SystemInit (void)
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{
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/* Add your system initialize code here.
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Do not use global variables because this function is called before
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reaching pre-main. RW section maybe overwritten afterwards. */
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
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SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
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(3UL << 11*2) ); /* set CP11 Full Access */
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#endif
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/* Disable Flash Access Cycle Auto-tuning, set access cycle for CPU @ 192MHz */
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/* The FMC_CYCCTL_FADIS_Msk bit is removed from BSP and gets unnecessary because it has fixed to 1 by ROMMAP on real chips (Both LAG018 and LAG033). */
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FMC->CYCCTL = (FMC->CYCCTL & ~FMC_CYCCTL_CYCLE_Msk) | (8 << FMC_CYCCTL_CYCLE_Pos);
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/* Configure power down bias, must set 1 before entering power down mode.
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So set it at the very beginning */
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CLK->LDOCTL |= CLK_LDOCTL_PDBIASEN_Msk;
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/* Hand over the control of PF.4~11 I/O function from RTC module to GPIO module */
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CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk;
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RTC->GPIOCTL0 &= ~(RTC_GPIOCTL0_CTLSEL0_Msk | RTC_GPIOCTL0_CTLSEL1_Msk |
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RTC_GPIOCTL0_CTLSEL2_Msk | RTC_GPIOCTL0_CTLSEL3_Msk);
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RTC->GPIOCTL1 &= ~(RTC_GPIOCTL1_CTLSEL4_Msk | RTC_GPIOCTL1_CTLSEL5_Msk |
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RTC_GPIOCTL1_CTLSEL6_Msk | RTC_GPIOCTL1_CTLSEL7_Msk);
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CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk;
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#if MBED_CONF_TARGET_HXT_PRESENT
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HXTInit();
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#endif
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#if MBED_CONF_TARGET_SPIM_CCM_ENABLE
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// Divert SRAM bank2 (32 KB) to CCM from SPIM cache
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// NOTE: C-runtime not initialized yet. Ensure no static memory (global variable) are accessed in function below.
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// NOTE: SPIM must keep enabled to run CCM mode.
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CLK_EnableModuleClock(SPIM_MODULE);
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SYS_ResetModule(SPIM_RST);
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SPIM_DISABLE_CACHE();
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SPIM_ENABLE_CCM();
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while (! SPIM_IS_CCM_EN());
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#endif
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}
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/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
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