mirror of https://github.com/ARMmbed/mbed-os.git
115 lines
4.2 KiB
C
Executable File
115 lines
4.2 KiB
C
Executable File
/* mbed Microcontroller Library
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*******************************************************************************
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* Copyright (c) 2023, MultiTech Systems
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of MultiTech nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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*/
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#include <string.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include "max32670.h"
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#include "gcr_regs.h"
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#include "mxc_sys.h"
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#include "pwrseq_regs.h"
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#define XDOT_ERFO_FREQ 24000000 // Change to 24000000 for xDot 1.5 Rev A
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void SystemCoreClockUpdateXdot(void)
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{
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uint32_t base_freq, div, clk_src;
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// Get the clock source and frequency
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clk_src = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL);
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switch (clk_src)
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{
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case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK:
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base_freq = EXTCLK_FREQ;
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break;
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case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO:
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base_freq = XDOT_ERFO_FREQ;
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break;
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case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO:
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base_freq = INRO_FREQ;
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break;
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case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO:
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base_freq = IPO_FREQ;
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break;
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case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO:
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base_freq = IBRO_FREQ;
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break;
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case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO:
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base_freq = ERTCO_FREQ;
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break;
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default:
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// Codes 001 and 111 are reserved.
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// This code should never execute, however, initialize to safe value.
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base_freq = HIRC_FREQ;
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break;
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}
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// Get the clock divider
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if (clk_src == MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO)
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{
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base_freq = base_freq >> ((MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_IPO_DIV)>> MXC_F_GCR_CLKCTRL_IPO_DIV_POS);
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}
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div = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_DIV) >> MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS;
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SystemCoreClock = base_freq >> div;
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}
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int PreInit(void)
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{
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return 0;
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}
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void SystemInit(void)
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{
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/* Make sure interrupts are enabled. */
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__enable_irq();
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#if (__FPU_PRESENT == 1)
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/* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
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/* Grant full access, per "Table B3-24 CPACR bit assignments". */
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/* DDI0403D "ARMv7-M Architecture Reference Manual" */
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SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
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__DSB();
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__ISB();
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#endif
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MXC_PWRSEQ->lpcn &= ~(1 << 31); // Ensure ERTCO is on
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MXC_SYS_Clock_Select(MXC_SYS_CLOCK_IPO);
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SystemCoreClockUpdateXdot();
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// Increase drive strength of I2C_SE bus and Mem Pwr En.
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// Note: Mem Pwr En doesn't help, higher drive strength on se i2c pins seems to though
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MXC_GPIO0->ds0 |= (1 << 6) | (1 << 7) | (1 << 24);
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MXC_GPIO0->ds1 |= (1 << 6) | (1 << 7) | (1 << 24);
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MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0);
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MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1);
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}
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