mirror of https://github.com/ARMmbed/mbed-os.git
259 lines
12 KiB
C
259 lines
12 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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// SPDX-License-Identifier: Apache-2.0
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#include "PeripheralPins.h"
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#include "PeripheralPinConfigs.h"
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/************RTC***************/
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const PinMap PinMap_RTC[] = {
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{NC, 0, 0},
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};
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/************ADC***************/
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const PinMap PinMap_ADC[] = {
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{NC, NC, 0}
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};
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/************DAC***************/
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const PinMap PinMap_DAC[] = {
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{NC, NC, 0}
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};
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/************I2C***************/
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const PinMap PinMap_I2C_SDA[] = {
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{AP3_PER_IOM0_SDA, IOM_0, (uint32_t) &g_AP3_PER_IOM0_SDA},
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{AP3_PER_IOM1_SDA, IOM_1, (uint32_t) &g_AP3_PER_IOM1_SDA},
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{AP3_PER_IOM2_SDA, IOM_2, (uint32_t) &g_AP3_PER_IOM2_SDA},
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{AP3_PER_IOM4_SDA, IOM_4, (uint32_t) &g_AP3_PER_IOM4_SDA},
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{AP3_PER_IOM5_SDA, IOM_5, (uint32_t) &g_AP3_PER_IOM5_SDA},
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#if defined (AM_PACKAGE_BGA)
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{AP3_PER_IOM3_SDA, IOM_3, (uint32_t) &g_AP3_PER_IOM3_SDA},
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#endif // defined (AM_PACKAGE_BGA)
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{NC, NC, 0}
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};
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const PinMap PinMap_I2C_SCL[] = {
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{AP3_PER_IOM0_SCL, IOM_0, (uint32_t) &g_AP3_PER_IOM0_SCL},
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{AP3_PER_IOM1_SCL, IOM_1, (uint32_t) &g_AP3_PER_IOM1_SCL},
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{AP3_PER_IOM2_SCL, IOM_2, (uint32_t) &g_AP3_PER_IOM2_SCL},
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{AP3_PER_IOM4_SCL, IOM_4, (uint32_t) &g_AP3_PER_IOM4_SCL},
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{AP3_PER_IOM5_SCL, IOM_5, (uint32_t) &g_AP3_PER_IOM5_SCL},
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#if defined (AM_PACKAGE_BGA)
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{AP3_PER_IOM3_SCL, IOM_3, (uint32_t) &g_AP3_PER_IOM3_SCL},
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#endif // defined (AM_PACKAGE_BGA)
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{NC, NC, 0}
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};
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/************UART***************/
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const PinMap PinMap_UART_TX[] = {
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{AP3_PER_UART0_TX_1, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_1},
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{AP3_PER_UART0_TX_7, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_7},
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{AP3_PER_UART0_TX_16, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_16},
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{AP3_PER_UART0_TX_20, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_20},
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{AP3_PER_UART0_TX_22, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_22},
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{AP3_PER_UART0_TX_26, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_26},
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{AP3_PER_UART0_TX_28, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_28},
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{AP3_PER_UART0_TX_39, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_39},
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{AP3_PER_UART0_TX_41, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_41},
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{AP3_PER_UART0_TX_44, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_44},
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{AP3_PER_UART0_TX_48, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_48},
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{AP3_PER_UART1_TX_8, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_8},
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{AP3_PER_UART1_TX_10, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_10},
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{AP3_PER_UART1_TX_12, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_12},
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{AP3_PER_UART1_TX_14, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_14},
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{AP3_PER_UART1_TX_18, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_18},
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{AP3_PER_UART1_TX_20, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_20},
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{AP3_PER_UART1_TX_24, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_24},
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{AP3_PER_UART1_TX_39, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_39},
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#if defined (AM_PACKAGE_BGA)
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{AP3_PER_UART0_TX_30, UART_0, (uint32_t) &g_AP3_PER_UART0_TX_30},
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{AP3_PER_UART1_TX_35, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_35},
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{AP3_PER_UART1_TX_37, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_37},
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{AP3_PER_UART1_TX_42, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_42},
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{AP3_PER_UART1_TX_46, UART_1, (uint32_t) &g_AP3_PER_UART1_TX_46},
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#endif // defined (AM_PACKAGE_BGA)
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{NC, NC, 0}
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};
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const PinMap PinMap_UART_RX[] = {
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{AP3_PER_UART0_RX_2, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_2},
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{AP3_PER_UART0_RX_11, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_11},
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{AP3_PER_UART0_RX_17, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_17},
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{AP3_PER_UART0_RX_21, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_21},
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{AP3_PER_UART0_RX_23, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_23},
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{AP3_PER_UART0_RX_27, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_27},
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{AP3_PER_UART0_RX_29, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_29},
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{AP3_PER_UART0_RX_40, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_40},
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{AP3_PER_UART0_RX_49, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_49},
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{AP3_PER_UART1_RX_2, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_2},
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{AP3_PER_UART1_RX_4, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_4},
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{AP3_PER_UART1_RX_9, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_9},
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{AP3_PER_UART1_RX_13, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_13},
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{AP3_PER_UART1_RX_15, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_15},
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{AP3_PER_UART1_RX_19, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_19},
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{AP3_PER_UART1_RX_21, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_21},
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{AP3_PER_UART1_RX_25, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_25},
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{AP3_PER_UART1_RX_40, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_40},
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{AP3_PER_UART1_RX_47, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_47},
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#if defined (AM_PACKAGE_BGA)
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{AP3_PER_UART0_RX_31, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_31},
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{AP3_PER_UART0_RX_34, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_34},
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{AP3_PER_UART0_RX_45, UART_0, (uint32_t) &g_AP3_PER_UART0_RX_45},
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{AP3_PER_UART1_RX_36, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_36},
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{AP3_PER_UART1_RX_38, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_38},
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{AP3_PER_UART1_RX_43, UART_1, (uint32_t) &g_AP3_PER_UART1_RX_43},
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#endif // defined (AM_PACKAGE_BGA)
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{NC, NC, 0}
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};
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const PinMap PinMap_UART_RTS[] = {
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{3, UART_0, AM_HAL_PIN_3_UART0RTS},
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{5, UART_0, AM_HAL_PIN_5_UART0RTS},
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{13, UART_0, AM_HAL_PIN_13_UART0RTS},
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{18, UART_0, AM_HAL_PIN_18_UART0RTS},
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{41, UART_0, AM_HAL_PIN_41_UART0RTS},
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{10, UART_1, AM_HAL_PIN_10_UART1RTS},
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{16, UART_1, AM_HAL_PIN_16_UART1RTS},
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{20, UART_1, AM_HAL_PIN_20_UART1RTS},
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{41, UART_1, AM_HAL_PIN_41_UART1RTS},
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{44, UART_1, AM_HAL_PIN_44_UART1RTS},
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#if defined (AM_PACKAGE_BGA)
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{34, UART_0, AM_HAL_PIN_34_UART0RTS},
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{35, UART_0, AM_HAL_PIN_35_UART0RTS},
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{37, UART_0, AM_HAL_PIN_37_UART0RTS},
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{30, UART_1, AM_HAL_PIN_30_UART1RTS},
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{31, UART_1, AM_HAL_PIN_31_UART1RTS},
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{34, UART_1, AM_HAL_PIN_34_UART1RTS},
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#endif // defined (AM_PACKAGE_BGA)
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{NC, NC, 0}
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};
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const PinMap PinMap_UART_CTS[] = {
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{4, UART_0, AM_HAL_PIN_4_UART0CTS},
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{6, UART_0, AM_HAL_PIN_6_UART0CTS},
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{12, UART_0, AM_HAL_PIN_12_UART0CTS},
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{24, UART_0, AM_HAL_PIN_24_UART0CTS},
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{29, UART_0, AM_HAL_PIN_29_UART0CTS},
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{11, UART_1, AM_HAL_PIN_11_UART1CTS},
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{17, UART_1, AM_HAL_PIN_17_UART1CTS},
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{21, UART_1, AM_HAL_PIN_21_UART1CTS},
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{26, UART_1, AM_HAL_PIN_26_UART1CTS},
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{29, UART_1, AM_HAL_PIN_29_UART1CTS},
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#if defined (AM_PACKAGE_BGA)
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{33, UART_0, AM_HAL_PIN_33_UART0CTS},
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{36, UART_0, AM_HAL_PIN_36_UART0CTS},
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{38, UART_0, AM_HAL_PIN_38_UART0CTS},
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{32, UART_1, AM_HAL_PIN_32_UART1CTS},
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{36, UART_1, AM_HAL_PIN_36_UART1CTS},
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{45, UART_1, AM_HAL_PIN_45_UART1CTS},
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#endif // defined (AM_PACKAGE_BGA)
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{NC, NC, 0}
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};
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/************SPI***************/
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const PinMap PinMap_SPI_SCLK[] = {
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{AP3_PER_IOM0_SCK, IOM_0, (uint32_t) &g_AP3_PER_IOM0_SCK},
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{AP3_PER_IOM1_SCK, IOM_1, (uint32_t) &g_AP3_PER_IOM1_SCK},
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{AP3_PER_IOM2_SCK, IOM_2, (uint32_t) &g_AP3_PER_IOM2_SCK},
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{AP3_PER_IOM4_SCK, IOM_4, (uint32_t) &g_AP3_PER_IOM4_SCK},
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{AP3_PER_IOM5_SCK, IOM_5, (uint32_t) &g_AP3_PER_IOM5_SCK},
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#if defined (AM_PACKAGE_BGA)
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{AP3_PER_IOM3_SCK, IOM_3, (uint32_t) &g_AP3_PER_IOM3_SCK},
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#endif // defined (AM_PACKAGE_BGA)
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{NC, NC, 0}
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};
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const PinMap PinMap_SPI_MOSI[] = {
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{AP3_PER_IOM0_MOSI, IOM_0, (uint32_t) &g_AP3_PER_IOM0_MOSI},
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{AP3_PER_IOM1_MOSI, IOM_1, (uint32_t) &g_AP3_PER_IOM1_MOSI},
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{AP3_PER_IOM2_MOSI, IOM_2, (uint32_t) &g_AP3_PER_IOM2_MOSI},
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{AP3_PER_IOM4_MOSI, IOM_4, (uint32_t) &g_AP3_PER_IOM4_MOSI},
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{AP3_PER_IOM5_MOSI, IOM_5, (uint32_t) &g_AP3_PER_IOM5_MOSI},
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#if defined (AM_PACKAGE_BGA)
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{AP3_PER_IOM3_MOSI, IOM_3, (uint32_t) &g_AP3_PER_IOM3_MOSI},
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#endif // defined (AM_PACKAGE_BGA)
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{NC, NC, 0}
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};
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const PinMap PinMap_SPI_MISO[] = {
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{AP3_PER_IOM0_MISO, IOM_0, (uint32_t) &g_AP3_PER_IOM0_MISO},
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{AP3_PER_IOM1_MISO, IOM_1, (uint32_t) &g_AP3_PER_IOM1_MISO},
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{AP3_PER_IOM2_MISO, IOM_2, (uint32_t) &g_AP3_PER_IOM2_MISO},
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{AP3_PER_IOM4_MISO, IOM_4, (uint32_t) &g_AP3_PER_IOM4_MISO},
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{AP3_PER_IOM5_MISO, IOM_5, (uint32_t) &g_AP3_PER_IOM5_MISO},
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#if defined (AM_PACKAGE_BGA)
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{AP3_PER_IOM3_MISO, IOM_3, (uint32_t) &g_AP3_PER_IOM3_MISO},
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#endif // defined (AM_PACKAGE_BGA)
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{NC, NC, 0}
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};
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const PinMap PinMap_SPI_SSEL[] = {
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{AP3_PER_NCE_0, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_0},
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{AP3_PER_NCE_1, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_1},
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{AP3_PER_NCE_2, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_2},
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{AP3_PER_NCE_3, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_3},
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{AP3_PER_NCE_4, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_4},
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{AP3_PER_NCE_7, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_7},
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{AP3_PER_NCE_8, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_8},
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{AP3_PER_NCE_9, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_9},
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{AP3_PER_NCE_10, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_10},
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{AP3_PER_NCE_11, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_11},
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{AP3_PER_NCE_12, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_12},
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{AP3_PER_NCE_13, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_13},
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{AP3_PER_NCE_14, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_14},
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{AP3_PER_NCE_15, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_15},
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{AP3_PER_NCE_16, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_16},
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{AP3_PER_NCE_17, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_17},
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{AP3_PER_NCE_18, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_18},
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{AP3_PER_NCE_19, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_19},
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{AP3_PER_NCE_20, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_20},
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{AP3_PER_NCE_21, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_21},
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{AP3_PER_NCE_22, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_22},
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{AP3_PER_NCE_23, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_23},
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{AP3_PER_NCE_24, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_24},
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{AP3_PER_NCE_25, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_25},
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{AP3_PER_NCE_26, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_26},
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{AP3_PER_NCE_27, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_27},
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{AP3_PER_NCE_28, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_28},
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{AP3_PER_NCE_29, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_29},
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{AP3_PER_NCE_41, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_41},
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{AP3_PER_NCE_44, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_44},
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{AP3_PER_NCE_47, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_47},
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{AP3_PER_NCE_48, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_48},
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{AP3_PER_NCE_49, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_49},
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#if defined (AM_PACKAGE_BGA)
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{AP3_PER_NCE_30, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_30},
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{AP3_PER_NCE_31, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_31},
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{AP3_PER_NCE_32, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_32},
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{AP3_PER_NCE_33, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_33},
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{AP3_PER_NCE_34, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_34},
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{AP3_PER_NCE_35, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_35},
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{AP3_PER_NCE_36, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_36},
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{AP3_PER_NCE_37, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_37},
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{AP3_PER_NCE_38, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_38},
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{AP3_PER_NCE_42, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_42},
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{AP3_PER_NCE_43, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_43},
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{AP3_PER_NCE_45, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_45},
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{AP3_PER_NCE_46, IOM_ANY, (uint32_t) &g_AP3_PER_NCE_46},
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#endif // defined (AM_PACKAGE_BGA)
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{NC, NC, 0}
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};
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/************PWM***************/
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const PinMap PinMap_PWM[] = {
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{NC, NC, 0}
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};
|