mirror of https://github.com/ARMmbed/mbed-os.git
109 lines
3.5 KiB
C
109 lines
3.5 KiB
C
/*
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* Copyright (c) 2013-2018, ARM Limited, All Rights Reserved
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* \file pn512_irq.h
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* \copyright Copyright (c) ARM Ltd 2013
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* \author Donatien Garnier
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*/
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#ifndef PN512_IRQ_H_
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#define PN512_IRQ_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "stack/nfc_common.h"
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#include "pn512.h"
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#include "pn512_registers.h"
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#define PN512_IRQ_TX (1<<6)
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#define PN512_IRQ_RX (1<<5)
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#define PN512_IRQ_IDLE (1<<4)
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#define PN512_IRQ_HIGH_ALERT (1<<3)
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#define PN512_IRQ_LOW_ALERT (1<<2)
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#define PN512_IRQ_ERR (1<<1)
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#define PN512_IRQ_TIMER (1<<0)
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#define PN512_IRQ_SIGIN (1<<(4+8))
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#define PN512_IRQ_MODE (1<<(3+8))
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#define PN512_IRQ_CRC (1<<(2+8))
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#define PN512_IRQ_RF_ON (1<<(1+8))
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#define PN512_IRQ_RF_OFF (1<<(0+8))
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#define PN512_IRQ_NONE 0x00
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#define PN512_IRQ_ALL 0x1F7F
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#define PN512_REG_COMIEN_MASK 0x7F
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#define PN512_REG_COMIEN_VAL 0x00
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#define PN512_REG_DIVIEN_MASK 0x1F
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#define PN512_REG_DIVIEN_VAL 0x80
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#define PN512_REG_COMIRQ_MASK 0x7F
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#define PN512_REG_COMIRQ_CLEAR 0x00
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#define PN512_REG_DIVIRQ_MASK 0x1F
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#define PN512_REG_DIVIRQ_CLEAR 0x00
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/** \internal Set IRQ enable registers
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* \param pPN512 pointer to pn512_t structure
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* \param irqs MSB is DIVIEN value, LSB is COMIEN value
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*/
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static inline void pn512_irq_set(pn512_t *pPN512, uint16_t irqs) //ORed
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{
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pn512_register_write(pPN512, PN512_REG_COMIEN, PN512_REG_COMIEN_VAL | (PN512_REG_COMIEN_MASK & (irqs & 0xFF)));
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pn512_register_write(pPN512, PN512_REG_DIVIEN, PN512_REG_DIVIEN_VAL | (PN512_REG_DIVIEN_MASK & (irqs >> 8)));
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pPN512->irqsEn = irqs;
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}
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/** \internal Get IRQ enable registers
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* \param pPN512 pointer to pn512_t structure
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* \return MSB is DIVIEN value, LSB is COMIEN value
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*/
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static inline uint16_t pn512_irq_enabled(pn512_t *pPN512) //ORed
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{
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return pPN512->irqsEn /*(pn512_register_read(pPN512, PN512_REG_COMIEN_VAL) & PN512_REG_COMIEN_MASK)
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| ((pn512_register_read(pPN512, PN512_REG_DIVIEN_VAL) & PN512_REG_DIVIEN_MASK) << 8)*/;
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}
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/** \internal Get IRQ status registers (masked with enabled IRQ register)
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* \param pPN512 pointer to pn512_t structure
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* \return MSB is DIVIRQ value, LSB is COMIRQ value
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*/
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static inline uint16_t pn512_irq_get(pn512_t *pPN512) //ORed
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{
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return ((pn512_register_read(pPN512, PN512_REG_COMIRQ) & PN512_REG_COMIEN_MASK)
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| ((pn512_register_read(pPN512, PN512_REG_DIVIRQ) & PN512_REG_DIVIEN_MASK) << 8)) & pPN512->irqsEn;
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}
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/** \internal Clear some interrupts
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* \param pPN512 pointer to pn512_t structure
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* \param irqs MSB is DIVIEN value, LSB is COMIEN value
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*/
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static inline void pn512_irq_clear(pn512_t *pPN512, uint16_t irqs)
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{
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pn512_register_write(pPN512, PN512_REG_COMIRQ, PN512_REG_COMIRQ_CLEAR | (PN512_REG_COMIRQ_MASK & (irqs & 0xFF)));
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pn512_register_write(pPN512, PN512_REG_DIVIRQ, PN512_REG_DIVIRQ_CLEAR | (PN512_REG_DIVIRQ_MASK & (irqs >> 8)));
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* PN512_IRQ_H_ */
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