mirror of https://github.com/ARMmbed/mbed-os.git
87 lines
3.2 KiB
C
87 lines
3.2 KiB
C
/***************************************************************************//**
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* \file cyip_hsiom.h
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*
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* \brief
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* HSIOM IP definitions
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*
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* \note
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* Generator version: 1.2.0.117
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* Database revision: rev#1034984
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*
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********************************************************************************
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* \copyright
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* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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*******************************************************************************/
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#ifndef _CYIP_HSIOM_H_
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#define _CYIP_HSIOM_H_
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#include "cyip_headers.h"
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/*******************************************************************************
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* HSIOM
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*******************************************************************************/
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#define HSIOM_PRT_SECTION_SIZE 0x00000010UL
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#define HSIOM_SECTION_SIZE 0x00004000UL
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/**
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* \brief HSIOM port registers (HSIOM_PRT)
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*/
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typedef struct {
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__IOM uint32_t PORT_SEL0; /*!< 0x00000000 Port selection 0 */
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__IOM uint32_t PORT_SEL1; /*!< 0x00000004 Port selection 1 */
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__IM uint32_t RESERVED[2];
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} HSIOM_PRT_Type; /*!< Size = 16 (0x10) */
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/**
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* \brief High Speed IO Matrix (HSIOM) (HSIOM)
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*/
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typedef struct {
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HSIOM_PRT_Type PRT[128]; /*!< 0x00000000 HSIOM port registers */
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__IM uint32_t RESERVED[1536];
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__IOM uint32_t AMUX_SPLIT_CTL[64]; /*!< 0x00002000 AMUX splitter cell control */
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} HSIOM_Type; /*!< Size = 8448 (0x2100) */
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/* HSIOM_PRT.PORT_SEL0 */
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#define HSIOM_PRT_PORT_SEL0_IO0_SEL_Pos 0UL
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#define HSIOM_PRT_PORT_SEL0_IO0_SEL_Msk 0x1FUL
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#define HSIOM_PRT_PORT_SEL0_IO1_SEL_Pos 8UL
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#define HSIOM_PRT_PORT_SEL0_IO1_SEL_Msk 0x1F00UL
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#define HSIOM_PRT_PORT_SEL0_IO2_SEL_Pos 16UL
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#define HSIOM_PRT_PORT_SEL0_IO2_SEL_Msk 0x1F0000UL
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#define HSIOM_PRT_PORT_SEL0_IO3_SEL_Pos 24UL
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#define HSIOM_PRT_PORT_SEL0_IO3_SEL_Msk 0x1F000000UL
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/* HSIOM_PRT.PORT_SEL1 */
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#define HSIOM_PRT_PORT_SEL1_IO4_SEL_Pos 0UL
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#define HSIOM_PRT_PORT_SEL1_IO4_SEL_Msk 0x1FUL
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#define HSIOM_PRT_PORT_SEL1_IO5_SEL_Pos 8UL
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#define HSIOM_PRT_PORT_SEL1_IO5_SEL_Msk 0x1F00UL
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#define HSIOM_PRT_PORT_SEL1_IO6_SEL_Pos 16UL
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#define HSIOM_PRT_PORT_SEL1_IO6_SEL_Msk 0x1F0000UL
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#define HSIOM_PRT_PORT_SEL1_IO7_SEL_Pos 24UL
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#define HSIOM_PRT_PORT_SEL1_IO7_SEL_Msk 0x1F000000UL
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/* HSIOM.AMUX_SPLIT_CTL */
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#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Pos 0UL
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#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk 0x1UL
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#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Pos 1UL
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#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk 0x2UL
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#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_S0_Pos 2UL
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#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_S0_Msk 0x4UL
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#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos 4UL
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#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk 0x10UL
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#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Pos 5UL
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#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk 0x20UL
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#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_S0_Pos 6UL
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#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_S0_Msk 0x40UL
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#endif /* _CYIP_HSIOM_H_ */
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/* [] END OF FILE */
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