/**************************************************************************//**
* @file partition_M2351.c
* @version V3.00
* $Revision: 2 $
* $Date: 16/12/28 1:08p $
* @brief SAU configuration for secure/nonsecure region settings.
*
* @note
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#ifndef PARTITION_M2351
#define PARTITION_M2351
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
*/
/*
// Secure Attribute Unit (SAU) Control
*/
#define SAU_INIT_CTRL 1
/*
// Enable SAU
// To enable Secure Attribute Unit (SAU).
*/
#define SAU_INIT_CTRL_ENABLE 1
/*
// All Memory Attribute When SAU is disabled
// <0=> All Memory is Secure
// <1=> All Memory is Non-Secure
// To set the ALLNS bit in SAU CTRL.
// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
*/
#define SAU_INIT_CTRL_ALLNS 0
/*
//
*/
/*
// Enable and Set Secure/Non-Secure region
*/
#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
/*
// SAU Region 0
// Setup SAU Region 0
*/
#define SAU_INIT_REGION0 1
/*
// Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START0 0x0003F000 /* start address of SAU region 0 */
/*
// End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END0 0x0003FFFF /* end address of SAU region 0 */
/*
// Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC0 1
/*
//
*/
/*
// SAU Region 1
// Setup SAU Region 1
*/
#define SAU_INIT_REGION1 1
/*
// Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START1 0x10040000
/*
// End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END1 0x1007FFFF
/*
// Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC1 0
/*
//
*/
/*
// SAU Region 2
// Setup SAU Region 2
*/
#define SAU_INIT_REGION2 0
/*
// Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START2 0x2000F000
/*
// End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END2 0x2000FFFF
/*
// Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC2 1
/*
//
*/
/*
// SAU Region 3
// Setup SAU Region 3
*/
#define SAU_INIT_REGION3 1
/*
// Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START3 0x30006000
/*
// End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END3 0x30017FFF
/*
// Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC3 0
/*
//
*/
/*
// SAU Region 4
// Setup SAU Region 4
*/
#define SAU_INIT_REGION4 1
/*
// Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START4 0x50000000 /* start address of SAU region 4 */
/*
// End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END4 0x5FFFFFFF /* end address of SAU region 4 */
/*
// Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC4 0
/*
//
*/
/*
// SAU Region 5
// Setup SAU Region 5
*/
#define SAU_INIT_REGION5 1
/*
// Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START5 0x00807C00
/*
// End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END5 0x00807FFF
/*
// Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC5 1
/*
//
*/
/*
// SAU Region 6
// Setup SAU Region 6
*/
#define SAU_INIT_REGION6 0
/*
// Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START6 0x00000000
/*
// End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END6 0x00000000
/*
// Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC6 0
/*
//
*/
/*
// SAU Region 7
// Setup SAU Region 7
*/
#define SAU_INIT_REGION7 0
/*
// Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START7 0x00000000
/*
// End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END7 0x00000000
/*
// Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC7 0
/*
//
*/
/*
//
*/
/*
// Setup behavior of Sleep and Exception Handling
*/
#define SCB_CSR_AIRCR_INIT 1
/*
// Deep Sleep can be enabled by
// <0=>Secure and Non-Secure state
// <1=>Secure state only
// Value for SCB->CSR register bit DEEPSLEEPS
*/
#define SCB_CSR_DEEPSLEEPS_VAL 0
/*
// System reset request accessible from
// <0=> Secure and Non-Secure state
// <1=> Secure state only
// Value for SCB->AIRCR register bit SYSRESETREQS
*/
#define SCB_AIRCR_SYSRESETREQS_VAL 0
/*
// Priority of Non-Secure exceptions is
// <0=> Not altered
// <1=> Lowered to 0x80-0xFF
// Value for SCB->AIRCR register bit PRIS
*/
#define SCB_AIRCR_PRIS_VAL 0
/* Assign HardFault to be always secure for safe */
#define SCB_AIRCR_BFHFNMINS_VAL 0
/*
//
*/
/*
// Assign Interrupt to Secure or Non-secure Vector
*/
/*
Initialize ITNS 0 (Interrupts 0..31)
*/
#define NVIC_INIT_ITNS0 1
/*
// BODOUT <0=> Secure <1=> Non-Secure
// IRC <0=> Secure <1=> Non-Secure
// PWRWU_ <0=> Secure <1=> Non-Secure
// SRAM_PERR <0=> Secure <1=> Non-Secure
// CLKFAIL <0=> Secure <1=> Non-Secure
// RTC <0=> Secure <1=> Non-Secure
// TAMPER <0=> Secure <1=> Non-Secure
// WDT <0=> Secure <1=> Non-Secure
// WWDT <0=> Secure <1=> Non-Secure
// EINT0 <0=> Secure <1=> Non-Secure
// EINT1 <0=> Secure <1=> Non-Secure
// EINT2 <0=> Secure <1=> Non-Secure
// EINT3 <0=> Secure <1=> Non-Secure
// EINT4 <0=> Secure <1=> Non-Secure
// EINT5 <0=> Secure <1=> Non-Secure
// GPA <0=> Secure <1=> Non-Secure
// GPB <0=> Secure <1=> Non-Secure
// GPC <0=> Secure <1=> Non-Secure
// GPD <0=> Secure <1=> Non-Secure
// GPE <0=> Secure <1=> Non-Secure
// GPF <0=> Secure <1=> Non-Secure
// SPI0 <0=> Secure <1=> Non-Secure
// SPI1 <0=> Secure <1=> Non-Secure
// BRAKE0 <0=> Secure <1=> Non-Secure
// PWM0_P0 <0=> Secure <1=> Non-Secure
// PWM0_P1 <0=> Secure <1=> Non-Secure
// PWM0_P2 <0=> Secure <1=> Non-Secure
// BRAKE1 <0=> Secure <1=> Non-Secure
// PWM1_P0 <0=> Secure <1=> Non-Secure
// PWM1_P1 <0=> Secure <1=> Non-Secure
// PWM1_P2 <0=> Secure <1=> Non-Secure
//
*/
#define NVIC_INIT_ITNS0_VAL 0x3F0040
/*
Initialize ITNS 1 (Interrupts 0..31)
*/
#define NVIC_INIT_ITNS1 1
/*
// TMR0 <0=> Secure <1=> Non-Secure
// TMR1 <0=> Secure <1=> Non-Secure
// TMR2 <0=> Secure <1=> Non-Secure
// TMR3 <0=> Secure <1=> Non-Secure
// UART0 <0=> Secure <1=> Non-Secure
// UART1 <0=> Secure <1=> Non-Secure
// I2C0 <0=> Secure <1=> Non-Secure
// I2C1 <0=> Secure <1=> Non-Secure
// PDMA0 is secure only
// DAC <0=> Secure <1=> Non-Secure
// EADC0 <0=> Secure <1=> Non-Secure
// EADC1 <0=> Secure <1=> Non-Secure
// ACMP01 <0=> Secure <1=> Non-Secure
// EADC2 <0=> Secure <1=> Non-Secure
// EADC3 <0=> Secure <1=> Non-Secure
// UART2 <0=> Secure <1=> Non-Secure
// UART3 <0=> Secure <1=> Non-Secure
// SPI2 <0=> Secure <1=> Non-Secure
// SPI3 <0=> Secure <1=> Non-Secure
// USBD <0=> Secure <1=> Non-Secure
// USBH <0=> Secure <1=> Non-Secure
// USBOTG <0=> Secure <1=> Non-Secure
// CAN0 <0=> Secure <1=> Non-Secure
// SC0 <0=> Secure <1=> Non-Secure
// SC1 <0=> Secure <1=> Non-Secure
// SC2 <0=> Secure <1=> Non-Secure
// SPI4 <0=> Secure <1=> Non-Secure
//
*/
#define NVIC_INIT_ITNS1_VAL 0x1C
/*
Initialize ITNS 2 (Interrupts 0..31)
*/
#define NVIC_INIT_ITNS2 1
/*
// SDH0 <0=> Secure <1=> Non-Secure
// I2S0 <0=> Secure <1=> Non-Secure
// OPA0 <0=> Secure <1=> Non-Secure
// CRYPTO <0=> Secure <1=> Non-Secure
// GPG <0=> Secure <1=> Non-Secure
// UART4 <0=> Secure <1=> Non-Secure
// UART5 <0=> Secure <1=> Non-Secure
// USCI0 <0=> Secure <1=> Non-Secure
// USCI1 <0=> Secure <1=> Non-Secure
// BPWM0 <0=> Secure <1=> Non-Secure
// BPWM1 <0=> Secure <1=> Non-Secure
// ICAP <0=> Secure <1=> Non-Secure
// I2C2 <0=> Secure <1=> Non-Secure
// QEI0 <0=> Secure <1=> Non-Secure
// QEI1 <0=> Secure <1=> Non-Secure
// ECAP0 <0=> Secure <1=> Non-Secure
// ECAP1 <0=> Secure <1=> Non-Secure
// SDH1 <0=> Secure <1=> Non-Secure
// USBH <0=> Secure <1=> Non-Secure
//
*/
#define NVIC_INIT_ITNS2_VAL 0x000
/*
Initialize ITNS 3 (Interrupts 0..31)
*/
#define NVIC_INIT_ITNS3 1
/*
// SPI5 <0=> Secure <1=> Non-Secure
// DSRC <0=> Secure <1=> Non-Secure
// PDMA1 <0=> Secure <1=> Non-Secure
// SCU <0=> Secure <1=> Non-Secure
// LCD <0=> Secure <1=> Non-Secure
// TRNG <0=> Secure <1=> Non-Secure
*/
#define NVIC_INIT_ITNS3_VAL 0x0
/*
//
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/*
max 128 SAU regions.
SAU regions are defined in partition.h
*/
#define SAU_INIT_REGION(n) \
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
/**
\brief Setup a SAU Region
\details Writes the region information contained in SAU_Region to the
registers SAU_RNR, SAU_RBAR, and SAU_RLAR
*/
__STATIC_INLINE void TZ_SAU_Setup(void)
{
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
SAU_INIT_REGION(0);
#endif
#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
SAU_INIT_REGION(1);
#endif
#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
SAU_INIT_REGION(2);
#endif
#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
SAU_INIT_REGION(3);
#endif
#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
SAU_INIT_REGION(4);
#endif
#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
SAU_INIT_REGION(5);
#endif
#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
SAU_INIT_REGION(6);
#endif
#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
SAU_INIT_REGION(7);
#endif
/* repeat this for all possible SAU regions */
#endif /* defined (__SAUREGION_PRESENT ) && (__SAUREGION_PRESENT == 1U) */
#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
#endif
#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk)) |
((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
// SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)) |
// ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
// ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk) |
// ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk);
SCB->AIRCR = (0x05FA << 16) |
((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk) |
((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk);
#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
#if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U)
SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk)) |
((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk);
#endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */
#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
#endif
#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
#endif
#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
#endif
#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
#endif
/* repeat this for all possible ITNS elements */
}
#endif
/*
// Peripheral Secure Attribution Configuration
*/
/*
PNSSET0
*/
/*
// Module 0..31
// USBH <0=> Secure <1=> Non-Secure
// SD0 <0=> Secure <1=> Non-Secure
// SD1 <0=> Secure <1=> Non-Secure
// EBI <0=> Secure <1=> Non-Secure
// PDMA1 <0=> Secure <1=> Non-Secure
*/
#define SCU_INIT_PNSSET0_VAL 0x00000001
/*
PNSSET1
*/
/*
// Module 0..31
// CRC <0=> Secure <1=> Non-Secure
// CRPT <0=> Secure <1=> Non-Secure
*/
#define SCU_INIT_PNSSET1_VAL 0x00040000
/*
PNSSET2
*/
/*
// Module 0..31
// RTC <0=> Secure <1=> Non-Secure
// EADC <0=> Secure <1=> Non-Secure
// ACMP01 <0=> Secure <1=> Non-Secure
// OPA <0=> Secure <1=> Non-Secure
// DAC <0=> Secure <1=> Non-Secure
// I2S0 <0=> Secure <1=> Non-Secure
// OTG <0=> Secure <1=> Non-Secure
// TMR23 <0=> Secure <1=> Non-Secure
// PWM0 <0=> Secure <1=> Non-Secure
// PWM1 <0=> Secure <1=> Non-Secure
// BPWM0 <0=> Secure <1=> Non-Secure
// BPWM1 <0=> Secure <1=> Non-Secure
*/
#define SCU_INIT_PNSSET2_VAL 0x00020002
/*
PNSSET3
*/
/*
// Module 0..31
// SPI0 <0=> Secure <1=> Non-Secure
// SPI1 <0=> Secure <1=> Non-Secure
// SPI2 <0=> Secure <1=> Non-Secure
// SPI3 <0=> Secure <1=> Non-Secure
// SPI4 <0=> Secure <1=> Non-Secure
// SPI5 <0=> Secure <1=> Non-Secure
// UART0 <0=> Secure <1=> Non-Secure
// UART1 <0=> Secure <1=> Non-Secure
// UART2 <0=> Secure <1=> Non-Secure
// UART3 <0=> Secure <1=> Non-Secure
// UART4 <0=> Secure <1=> Non-Secure
// UART5 <0=> Secure <1=> Non-Secure
*/
#define SCU_INIT_PNSSET3_VAL 0x00010000
/*
PNSSET4
*/
/*
// Module 0..31
// I2C0 <0=> Secure <1=> Non-Secure
// I2C1 <0=> Secure <1=> Non-Secure
// I2C2 <0=> Secure <1=> Non-Secure
// SC0 <0=> Secure <1=> Non-Secure
// SC1 <0=> Secure <1=> Non-Secure
// SC2 <0=> Secure <1=> Non-Secure
*/
#define SCU_INIT_PNSSET4_VAL 0x00000000
/*
PNSSET5
*/
/*
// Module 0..31
// CAN0 <0=> Secure <1=> Non-Secure
// QEI0 <0=> Secure <1=> Non-Secure
// QEI1 <0=> Secure <1=> Non-Secure
// ECAP0 <0=> Secure <1=> Non-Secure
// ECAP1 <0=> Secure <1=> Non-Secure
// DSRC <0=> Secure <1=> Non-Secure
// LCD <0=> Secure <1=> Non-Secure
// TRNG <0=> Secure <1=> Non-Secure
*/
#define SCU_INIT_PNSSET5_VAL 0x00000000
/*
PNSSET6
*/
/*
// Module 0..31
// USBD <0=> Secure <1=> Non-Secure
// USCI0 <0=> Secure <1=> Non-Secure
// USCI1 <0=> Secure <1=> Non-Secure
*/
#define SCU_INIT_PNSSET6_VAL 0x00000000
/*
//
*/
/*
// GPIO Secure Attribution Configuration
*/
/*
IONSSET
*/
/*
// Bit 0..31
// PA <0=> Secure <1=> Non-Secure
// PB <0=> Secure <1=> Non-Secure
// PC <0=> Secure <1=> Non-Secure
// PD <0=> Secure <1=> Non-Secure
// PE <0=> Secure <1=> Non-Secure
// PF <0=> Secure <1=> Non-Secure
// PG <0=> Secure <1=> Non-Secure
*/
#define SCU_INIT_IONSSET_VAL 0x0000007F
/*
//
*/
/*
// SRAM Secure Attribution Configuration
*/
/*
SRAMNSSET
*/
/*
// Bit 0..31
// 0x00000000 ~ 0x00001FFF <0=> Secure <1=> Non-Secure
// 0x00002000 ~ 0x00003FFF <0=> Secure <1=> Non-Secure
// 0x00004000 ~ 0x00005FFF <0=> Secure <1=> Non-Secure
// 0x00006000 ~ 0x00007FFF <0=> Secure <1=> Non-Secure
// 0x00008000 ~ 0x00009FFF <0=> Secure <1=> Non-Secure
// 0x0000A000 ~ 0x0000BFFF <0=> Secure <1=> Non-Secure
// 0x0000C000 ~ 0x0000DFFF <0=> Secure <1=> Non-Secure
// 0x0000E000 ~ 0x0000FFFF <0=> Secure <1=> Non-Secure
// 0x00010000 ~ 0x00011FFF <0=> Secure <1=> Non-Secure
// 0x00012000 ~ 0x00013FFF <0=> Secure <1=> Non-Secure
// 0x00014000 ~ 0x00015FFF <0=> Secure <1=> Non-Secure
// 0x00016000 ~ 0x00017FFF <0=> Secure <1=> Non-Secure
// 0x00018000 ~ 0x00019FFF <0=> Secure <1=> Non-Secure
// 0x0001A000 ~ 0x0001BFFF <0=> Secure <1=> Non-Secure
// 0x0001C000 ~ 0x0001DFFF <0=> Secure <1=> Non-Secure
// 0x0001E000 ~ 0x0001FFFF <0=> Secure <1=> Non-Secure
*/
#define SCU_INIT_SRAMNSSET_VAL 0x00000FF8
/*
//
*/
/**
\brief Setup SCU Configuration Unit
\details
*/
__STATIC_INLINE void SCU_Setup(void)
{
SCU->PNSSET[0] = SCU_INIT_PNSSET0_VAL;
SCU->PNSSET[1] = SCU_INIT_PNSSET1_VAL;
SCU->PNSSET[2] = SCU_INIT_PNSSET2_VAL;
SCU->PNSSET[3] = SCU_INIT_PNSSET3_VAL;
SCU->PNSSET[4] = SCU_INIT_PNSSET4_VAL;
SCU->PNSSET[5] = SCU_INIT_PNSSET5_VAL;
SCU->PNSSET[6] = SCU_INIT_PNSSET6_VAL;
SCU->IONSSET = SCU_INIT_IONSSET_VAL;
SCU->SRAMNSSET = SCU_INIT_SRAMNSSET_VAL;
}
/*
// APROM Non-secure Base Address Configuration
*/
/*
NSBA
*/
/*
// Enable Non-secure Base Address
// To check active Non-secure base address.
*/
#define FMC_INIT_NSBA 1
/*
// NSBA <0x4000-0x7FFFF>
*/
#define FMC_INIT_NSBA_VAL 0x00040000
/*
//
//
*/
__STATIC_INLINE void FMC_NSBA_Setup(void)
{
/* Skip NSBA Setupt according config */
if(FMC_INIT_NSBA == 0)
return;
/* Check if NSBA value with current active NSBA */
if(SCU->FNSADDR != FMC_INIT_NSBA_VAL)
{
/* Unlock Protected Register */
SYS_UnlockReg();
/* Enable ISP and config update */
FMC->ISPCTL = FMC_ISPCTL_ISPEN_Msk | FMC_ISPCTL_CFGUEN_Msk;
/* Config Base of NSBA */
FMC->ISPADDR = 0x200800;
/* Read Non-secure base address config */
FMC->ISPCMD = FMC_ISPCMD_READ;
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
while(FMC->ISPTRG);
/* Setting NSBA when it is empty */
if(FMC->ISPDAT == 0xfffffffful)
{
FMC->ISPDAT = FMC_INIT_NSBA_VAL;
FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
while(FMC->ISPTRG);
/* Force Chip Reset to valid new setting */
SYS->IPRST0 = SYS_IPRST0_CHIPRST_Msk;
}
/* Fatal Error:
FMC NSBA setting is different to FMC_INIT_NSBA_VAL.
User must double confirm which one is wrong.
If user need to change NSBA config of FMC, user must do Mess-erase by
ISP or ICP.
*/
while(1);
}
}
#endif /* PARTITION_M2351 */