Commit Graph

1834 Commits (mbed-os-5.12.4)

Author SHA1 Message Date
jeromecoutant 78b0d9b11f STM32 astyle updates 2019-05-17 15:38:41 +01:00
Guillermo Alonso e6fcada930 added QSPI support to target RHOMBIO_L476DMW1K 2019-05-17 15:38:41 +01:00
M. Rahimi 9ad5fd34cc Enabled crash reporting for DISCO_F407VG on all other toolchains 2019-05-17 15:35:27 +01:00
M. Rahimi 01e35e009e Enabled crash reporting for DISCO_F407VG target 2019-05-17 15:35:27 +01:00
Laurent Meunier b262080045 Typo fix for MBED_APP_SIZE 2019-05-17 15:35:27 +01:00
Laurent Meunier f73e6cd55d Update FLASH_SIZE backup value
By default, FLASH_SIZE should be read from HW.
In case this is not the case, we define it here, as the size of FLASH
that is available to the application running on M4.
2019-05-17 15:35:27 +01:00
Laurent Meunier a677e43939 STM32WB: Update Flash size
the flash is shared and split between cortex-M4 that
runs (mbed-os) application and the cortex-M0+ that
runs the BLE firmware.

The 512K allocated to the application was a
conservative that can now be updated.

With recent up-to-date BLE firmware flashed @ 0x080CB000,
there should be 812K available to application.

But there are boards out there that don't have an up-to-date
firmware, so we're keeping an intermediate, safer,
application size of 768K.
2019-05-17 15:35:27 +01:00
Lin Gao 2b33d06276 Add option to keep post_binary_hook and make it default. It can be disabled by setting it to null 2019-05-17 15:35:27 +01:00
Lin Gao ef21cf108b Fix handoff issue from the bootloader to the application on MTS_DRAGONFLY_F411RE 2019-05-17 15:35:27 +01:00
mudassar-ublox 7bf5657219 cellular target name change for ublox cellular instance 2019-05-17 15:35:27 +01:00
Martin Kojtal 01391fa85a SDP_K1: Fix year change in the system clock 2019-05-03 12:24:48 +01:00
Malavika Sajikumar 0ab7ad99e3 Fixing alignment. 2019-05-03 12:24:48 +01:00
Malavika Sajikumar a182558ff3 AWAKE signal turned on at system init for SDP-K1 board.
- Setting AWAKE signal high in the SystemInit() to ensure VIO supply to daughter boards through SDP and Arduino connectors.
2019-05-03 12:24:48 +01:00
Malavika Sajikumar 45a2952fec Improvements made to PinNames.h of SDP-K1 board.
PinNames.h:
- Removing definition of Status LED.
- Redefining SPI and I2C pin names using Arduino pins names.
2019-05-03 12:24:48 +01:00
Juho Eskeli b0780563a8 STM32L4xx: IAR linker file updated to better use available memory 2019-05-03 12:24:48 +01:00
Deepika d7e53cdd7c Add missing boot stack size memory from heap calculation 2019-05-03 12:24:48 +01:00
Deepika f8367b4f7c Update linker script for using SRAM1 and SRAM2 in ARM To have the flexibilty in application; to use any of the section (data/bss/heap) without updating linker script in every use case, following decisions are made: 1. Fixed size and small sections moved to SRAM2 (32K) Vectors Crash data Remaining section - RW / ZI 2. Large memory space should be used for variable sections RW/ZI Heap - (Minimum - 0x12000) Stack - At bottom 2019-05-03 12:24:48 +01:00
Deepika 96c0d8fb64 uARM - Move heap region after IRAM1
ARM_LIB_HEAP start is aligned to IRAM1 end, hence should be placed next to
RW_IRAM1 i.e. no other region in between.
2019-04-24 13:37:42 +01:00
jeromecoutant 4e551b1e4b STM32: protect compilation when DEVICE_USTICKER is disabled 2019-04-24 13:37:42 +01:00
Vincent Veron 5c872a4c06 TARGET_STM32F7: Reset QSPI in default mode on abort for all versions.
This patch is missing in F7 HAL.
Fix #10049

Signed-off-by: Vincent Veron <vincent.veron@st.com>
2019-04-24 13:37:42 +01:00
Ashok Rao a07dbd7445 SPDX license identifier changed to Apache-2.0 2019-04-05 13:59:51 +01:00
Ashok Rao 731cd1633f Adding SPDX identifier 2019-04-05 13:59:49 +01:00
Ashok Rao f3f2cedbbf Adding STM32_F429 + S2_LP (WiSUN) as a new MTB target 2019-04-05 13:59:45 +01:00
Ashok Rao a71a08cbf5 Changing SPI flash's CS ine, Errata on SCH 2019-04-05 13:59:40 +01:00
Ashok Rao 997ad6c766 Pin map changes
Based on v1.1.0 of S2_LP MCB using STM32F429ZIT6.
2019-04-05 13:59:38 +01:00
Ashok Rao 00a1c93f89 Adding MTB aliases to PinNames 2019-04-05 13:59:35 +01:00
Ashok Rao 7632c9784d Adding STM S2_LP as a new target 2019-04-05 13:59:32 +01:00
Laurent Meunier c5b277f880 STM32WB: ADC INTERNAL CHANNEL reset after read
Internal channels use is enabling ADC "internal path" which needs
to be disabled after measurement.

Same applied here for WB family as was done for others in #10143.
2019-04-05 12:27:07 +01:00
Laurent Meunier defa75ae17 STM32WB: Only configure default peripherals in SetSysClock
Typically the RTC clock is configured by RTC driver itself.

RNG on the other hand is shared with M0+ core and it is expected that
M4 turns it on at boot time.
2019-04-05 12:27:07 +01:00
Laurent Meunier fee3faea3f STM32WB: disable debug lines when not needed
When doing so, do not disbale GPIO clocks as they may be used by other
drivers !

As a result, debug will be disabled by default, but can be enabled by
either modifying code or selecting MBED debug profile.
2019-04-05 12:27:07 +01:00
Laurent Meunier c0bfcec6d3 STM32WB: update deep sleep sequence
Review HSE clock initialization to match with latest CUBE firmware.
Also there is no need to set the full clock tree again after deep sleep exit.

With this change we get a stable deep sleep mode (when allowed by CORDIO stack).
2019-04-05 12:27:06 +01:00
Laurent Meunier 9cf03e3438 STM32WB: update GCC linker script to match with master 2019-04-05 12:27:06 +01:00
Laurent Meunier 5da83a2617 STM32WB: Add FLASH HW Semaphore
Because FLASH is a shared resource between the 2 STM32WB cores, SW needs
to acquire HW Semaphore before using the resource.
2019-04-05 12:27:06 +01:00
Laurent Meunier 92ef812e42 STM32WB: Add TRNG HW Semaphore
Because TRNG is a shared resource between the 2 STM32WB cores, SW needs
to acquire HW Semaphore before using the resource.
2019-04-05 12:27:06 +01:00
Laurent Meunier 07545a20d6 STM32WB: Add SPDX identifier to new files
also update the copyright year when needed
2019-04-05 12:27:06 +01:00
Laurent Meunier 615a9f6548 STM32WB: Update headers 2019-04-05 12:27:05 +01:00
Laurent Meunier 96f88c5022 STM32WB: ARM linker script update
There is no need to add FIRST attribute to MAPPING_TABLE as the default
ordering is alphabetical order.

With this change, we don't have any warning with MBED2 and the sections
are properly ordered anyway in BLE cases.
2019-04-05 12:27:05 +01:00
Laurent Meunier f903920f47 STM32WB: Fix ARM link error in mbed2
In case of mbed2, BLE feature is not built.

As there is a MAPPING_TABLE in BLE feature which is not compiled in case
of mbed2, the linker reported the below error

[ERROR] "C:/Data/Workspace/mbed/BUILD/test/NUCLEO_WB55RG/ARM/MBED_2/
.link_script.sct", line 65 (column 6): Error: L6236E:
No section matches selector - no section to be FIRST/LAST.

Solution is to check whether BLE is enabled.
2019-04-05 12:27:04 +01:00
Laurent Meunier 0dcddcea9b STM32WB: Adapt I2C timings
for now based on L4+ cubeMX inputs
2019-04-05 12:27:04 +01:00
Laurent Meunier 9e3d52d701 fixup! NUCLEO_WB55RG: add SDK files 2019-04-05 12:27:04 +01:00
Laurent Meunier 9345e5cbcb STM32WB: Add missing analogin_pinmap
This is required since PR #9449
commit
"Add HAL API for analog in pinmap"
2019-04-05 12:27:04 +01:00
Laurent Meunier 86c84050be Add WB support and CUBE FW version in readme.md 2019-04-05 12:27:04 +01:00
Laurent Meunier 91c08e3914 STM: fix minor warnings 2019-04-05 12:27:04 +01:00
Laurent Meunier 1a6cdf849f STM32WB: FIX LL RTC warning 2019-04-05 12:27:04 +01:00
Laurent Meunier e57771f375 STM32WB: Move STM32WB utilies from FEATURE_BLE to targets folder
These files are not BLE specific, but also needed for some clock setting
for instance.

In order to compile an MBED2 application, we need to move the files.
2019-04-05 12:27:04 +01:00
Laurent Meunier ee64f1543f NUCLEO_WB55RG: Rework Clock and sleep support
- move hw_conf.h file to targets/TARGET_STM/TARGET_STM32WB directory as
this is used also out of BLE feature.
- create a dedicated hal_deepsleep function as the behavior in WB is a lot
different from other existing STM32 targets
- update clock tree configuration to directly clock the entire tree @ 32MHz
out of HSE. This is needed as we want to let the M0 core running without
any change on M0-side of clocks when M4 enters /exits deep sleep.
2019-04-05 12:27:04 +01:00
Laurent Meunier b5c30756f1 NUCLEO_WB55RG: IAR, ARM and GCC linker files alignment
Align all scatter BLE shared memory declarations.
2019-04-05 12:27:03 +01:00
jeromecoutant f913a31ad2 NUCLEO_WB55RG: HAL API updates to get SLEEP, RTC and LPTICKER OK
- astyle OK
- file alignment with other families
- HSE, MSI, HSI clock support
- LPTICKER with RTC and LPTIM tested
2019-04-05 12:27:03 +01:00
bcostm f07d570137 NUCLEO_WB55RG: update STM common files
- Include RTC ll file from hal as in other families
- STM32WB: update Flash API driver
2019-04-05 12:27:03 +01:00
bcostm 658c8b6fdb NUCLEO_WB55RG: update mbed_rtx.h 2019-04-05 12:27:03 +01:00