Commit Graph

2525 Commits (mbed-os-5.11.4)

Author SHA1 Message Date
deepikabhavnani fdb1a4f311 Correct the dsp flag from no_dsp to nodsp 2019-02-08 16:50:27 +00:00
Naveen Kaje e7985fd07a tools: build_api_test: add test to detect when part overflows region size 2019-02-08 16:50:27 +00:00
Naveen Kaje 03558761e0 tools: check part size is not exceeding region size
If config is specified, check that part size is not
exceeding the region. Normally we now assume that
part.maxaddr() can be beyond end of rom.
2019-02-08 16:50:27 +00:00
Volodymyr Medvid 1676bd3e83 makefile export: create .link_options.txt with echo
$(file > $@.in, $(filter %.o, $^)) is not supported in GNU Make 3.81.
Create the linker response file with pipe redirect from echo command.
This is tested with Cygwin make and make 3.8.1 shipped with macOS.

Also, change the linker responce file name to .link_options.txt.
This is an internal file, not a build artifact.
2019-02-08 16:50:27 +00:00
Jimmy Brisson ddddb6f8a1 Implement Linker command/response files in make export 2019-02-08 16:50:27 +00:00
Michael Schwarcz 0f15c7ffe5 Fix cortex-m33-S armlink error
Add "-mfpu=none" compilation flag
2019-02-08 16:50:27 +00:00
Michael Schwarcz f869e9a144 Fix cortex-m33-S compile error
Compilation error was due to due to bug in gcc.py
2019-02-08 16:50:27 +00:00
Deepika 7020e6cd23 Correct typo no_dsp - nodsp
armclang - nodsp
armlink - no_dsp
2019-02-08 16:50:27 +00:00
Brian Daniels a56970499d Improve error message for exports for OS2-only targets 2019-02-08 16:50:27 +00:00
Brian Daniels 538b6825a7 Add missing space - coding style nit
Co-Authored-By: deepikabhavnani <deepika.bhavnani@arm.com>
2019-02-08 16:50:27 +00:00
deepikabhavnani 53f52f9e0e Set the DSP option as `E` for Cortex-M33 2019-02-08 16:50:27 +00:00
deepikabhavnani ddf5060ef9 Correct the floating+dsp options for Cortex-M processors
As per the IAR Development guide, below options for CPU are valid

1. Cortex-M33
2. Cortex-M33.no_dsp (core without integer DSP extension)
3. Cortex-M33.fp (floating-point unit with support for single precision)
4. Cortex-M33.no_se (core without support for TrustZone)
5. Cortex-M4
6. Cortex-M4F
7. Cortex-M7
8. Cortex-M7.fp.dp (floating-point unit with support for double precision)
9. Cortex-M7.fp.sp (floating-point unit with support for single precision)
2019-02-08 16:50:27 +00:00
deepikabhavnani 3493e3ef56 Update `cmse` flag based on core_arch instead of different cores 2019-02-08 16:50:27 +00:00
Deepika 39827e4fbb M2351: Update code to support IAR 8.x builds 2019-02-08 16:50:27 +00:00
deepikabhavnani c20bf95a51 Update IAR flags for Armv8M devices.
Cortex-M23 / Cortex-M33 CPU settings for baseline and mainline
profile (with optional floating and dsp options) updated.
2019-02-08 16:50:27 +00:00
Andriy.Lishchynskyi 3bf6e9afb0 Resolved code review comments 2019-02-08 16:50:27 +00:00
Jimmy Brisson ea074d0c71 Apply suggestions from code review
Co-Authored-By: Cypress-OpenOCD <39907069+Cypress-OpenOCD@users.noreply.github.com>
2019-02-08 16:50:27 +00:00
Andriy.Lishchynskyi a427d891fe Added copyright notes 2019-02-08 16:50:27 +00:00
Andriy.Lishchynskyi 9bae7c4288 Changes: - added new erase launch configuration - added new kits support - code cleanup 2019-02-08 16:50:27 +00:00
Andriy.Lishchynskyi e6ab529a1e Fix python3 compatibility issue 2019-02-08 16:50:27 +00:00
Andriy.Lishchynskyi 7314258275 Added GNU MCU Eclipse plug-in support 2019-02-08 16:50:27 +00:00
Andriy.Lishchynskyi 5b979148aa Reworked launch configuration creation mechanism - switched to single template. Specific data comes from the JSON file 2019-02-08 16:50:27 +00:00
Andriy.Lishchynskyi 900ba6c9b6 added support for debug and program launch configurations 2019-02-08 16:50:27 +00:00
deepikabhavnani 4419f62bb0 Change if statements to lookup tables 2019-02-08 16:50:27 +00:00
deepikabhavnani a8c9cf1322 Change DSP variant symbol to `E` from `D`(d-double floating point) 2019-02-08 16:50:27 +00:00
deepikabhavnani 46dbfd6199 GCC_ARM: Strip the -NS from core option before setting floating point options 2019-02-08 16:50:27 +00:00
deepikabhavnani d8d62238d2 Armc6 - Set floating point and CPU options for all core variants explicitly
Below are the options read from the toolchains/arm
armclang --target=arm-arm-none-eabi -mcpu=list
The following arguments to option 'mcpu' can be selected:
  -mcpu=cortex-m0
  -mcpu=cortex-m0plus
  -mcpu=cortex-m1
  -mcpu=cortex-m3
  -mcpu=cortex-m4
  -mcpu=cortex-m7
  -mcpu=cortex-m23
  -mcpu=cortex-m33
  ...

armlink --cpu=list
The following arguments to option 'cpu' can be selected:
 --cpu=Cortex-M0
 --cpu=Cortex-M0plus
 --cpu=Cortex-M1
 --cpu=Cortex-M1.os_extension
 --cpu=Cortex-M1.no_os_extension
 --cpu=Cortex-M4
 --cpu=Cortex-M4.no_fp
 --cpu=Cortex-M7
 --cpu=Cortex-M7.fp.sp
 --cpu=Cortex-M7.no_fp
 --cpu=Cortex-M23
 --cpu=Cortex-M33
 --cpu=Cortex-M33.no_fp
 --cpu=Cortex-M33.no_dsp
 --cpu=Cortex-M33.no_dsp.no_fp
...

armclang --target=arm-arm-none-eabi -mfpu=list
The following arguments to option 'mfpu' can be selected:
  -mfpu=fpv4-sp-d16
  -mfpu=fpv5-sp-d16
  -mfpu=fpv5-d16
...
2019-02-08 16:50:27 +00:00
deepikabhavnani 1c5eb39b05 Use core arch for setting secure/non-secure flags 2019-02-08 16:50:27 +00:00
Amir Cohen dd43030751 Add sd-driver example 2019-02-08 16:50:27 +00:00
jeromecoutant 8d4b54db12 STM32_gen_PeripheralPins.py v1.5
Use dedicated PinMap for each QSPI data line #9438
2019-02-08 16:50:27 +00:00
jeromecoutant 9563254658 STM32_gen_PeripheralPins.py v1.4
Minor updates:
- remove QSPI BK2
- beautifier edition
- use STM_MODE_ANALOG_ADC_CONTROL for L4 family
2019-02-08 16:50:27 +00:00
Jimmy Brisson 675b7bd4f6 Updated spm test runner wish short import variant
Co-Authored-By: cmonr <Cruz.Monrreal@arm.com>
2019-02-08 16:50:27 +00:00
Cruz Monrreal II 59262edf82 Simplified max/min condition 2019-02-08 16:50:27 +00:00
Cruz Monrreal II 792d13d395 Added flag to run_cmd Popen invocation to do default decoding 2019-02-08 16:50:27 +00:00
Cruz Monrreal II 755931de72 Added None check for min in config tools 2019-02-08 16:50:27 +00:00
Cruz Monrreal II 246f6fc305 In Py3.7, a reinit of a mock variable was needed. It seems that initializing mock variables in an object isn't enough 2019-02-08 16:50:27 +00:00
Cruz Monrreal II 5469c00e81 Added encoding to version check for Py3 compat 2019-02-08 16:50:27 +00:00
Cruz Monrreal II 8e169f2a06 Increased path for spm include. Py3 tests were not running as a result 2019-02-08 16:50:27 +00:00
Cruz Monrreal II 13ad6f6694 Added universal_newlines flag to Popen in pylint.py 2019-02-08 16:50:27 +00:00
Mahesh Mahadevan d1a610a33c MIMXRT1050_EVK: Add IAR support in the exporter
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2019-02-08 16:50:27 +00:00
Michal Paszta 2117c7f932 Add TLSSocket greentea tests.
TLSSocket tests based on existing TCPSocket greentea tests and TLSSocket icetea tests.
2019-02-08 16:50:27 +00:00
Volodymyr Medvid ced094f153 PSOC6.py: generate hex files with 16 bytes per row
DAPLink implementation on Cypress kits cannot handle hex files
with 64 bytes per row: refer to https://github.com/ARMmbed/DAPLink,
source/daplink/drag-n-drop/intelhex.c, hex_line_t struct, data field.
2019-02-08 16:48:59 +00:00
Volodymyr Medvid 5d819621e9 PSOC6: refactor M0 image merging, enable export to makefile
Rename the existing PSoC-specific m0_core_img key in targets.json
as a more generic hex_filename key. Update makefile exporter to select
the subset of resources.hex_files matching the hex_filename value.
Without this fix, multiple prebuilt CM0+ hex files are found in the
target resources and erroneously passed to the srec_cat tool.

The fix is generic so other targets that need post-build hex merging
can use this key to pass the correct image to srecord tool.

The fix also removes sub_target key: instead, rely hex_filename json
key to detect if the hex image merging needs to be done.
The sub_target is not used in mbed-os codebase for anything else.

It is possible to override the hex file name in mbed_app.json:
{
  "target_overrides": {
    "*": {
      "target.hex_filename": "my_custom_m0_image.hex"
    }
}
2019-02-08 16:48:59 +00:00
Volodymyr Medvid ecc9aa7bf2 PSOC6.py: do not require metadata during HEX merging
Replace hard-coded numeric offsets of PSoC 6 hex file sections
with sensible constants.
Do not attempt to update the checksum and metadata contents
if the sections are not found in the original HEX file.
2019-02-08 16:48:59 +00:00
Volodymyr Medvid 3fa2fb21cc PSOC6.py: remove silicon ID check
PSoC 6 hex files contain 4-byte chip ID at virtual offset 0x90500002
added by PSoC Creator or cymcuelftool from .cymeta ELF section.
merge_images compares chip ID in CM0+ and CM4 hex files and raises
an exception in case of mismatch. Chip ID is different for each MPN
(for example, 0xE2072100 for CY8C6347BZI-BLD53 and 0xE2062100 for
CY8C6247BZI-D54). CM0+ prebuilt images target CY8C6347BZI-BLD53
but should be compatible with other PSoC6 MPNs.
Remove the check to enable merging CM0+ images with CM4 applications
built for different MPNs, with empty or absent cymetadata.
2019-02-08 16:48:59 +00:00
Seppo Takalo 5bd99ec2d6 Fix spelling mistakes 2019-02-08 16:48:59 +00:00
Martin Kojtal 3f5c4de3b5 examples: fix incorrect target addition in 5.11.3rc 2019-01-26 20:58:49 +01:00
Kevin Gilbert 207aa6cfce Add empty en_phonet.
Required to run with aspell and comply with license changes
2019-01-25 14:29:59 +00:00
Martin Kojtal 672665ad1c travis: remove phonedat database
Not permissive license
2019-01-25 14:29:59 +00:00
deepikabhavnani 9a8d748fd3 Corrected the targets value in json file as CI uses real board names 2019-01-25 14:29:59 +00:00