This commit implements a SPI mode which will offer better performance
thanks to usage of Lower Layer API which use fewer registers access,
at the cost of lower robustness (no error management).
There is an easy default implementation of spi_master_block_write that
just calls spi_master_write in a loop, so the default implementation
of spi_master_block_write has been added to all targets.
Default timeout of 10ms was reported as an issue in #4300
There seems to be conditions or use cases where the system is loaded with
higher priority tasks so that SPI transfer would be delayed more than 10ms.
Recommendation from MBED team is to not implement any timeout at all as
there is no defined API in MBED to inform application of error cases.
In case the selected frequency is higher than the requested one, it is
better to send a debug warning rather than an blocking error.
In case of such warning, user may need to redefine the clock tree setting
at higher level (reducing peripheral's input clocks during init phase).
In case of prescaler_rank was 0, a -1 index was being used,
which resulted in initialization of the Init.BaudRatePrescaler with
random values.
Now let's better check index and avoid -1 operation, so that prescaler_rank
can be only from 0 to "last_index".
In case Rx is not initiliased its content might be random from stack.
This is causing problem in case of 8 bits read only as the left-side 8 bits
of the returned int value may contain this random byte data. This was for
instance detected when using SDFileSystem Lib.
ASYNCH SPI transfer support has been added based on STM HAL services.
To have both ASYNCH and SYNCH work together, we're also moving the
write API to STM HAL instead of direct registers access.
the SPI_ASYNCH feature has been already activated for STM32F4.
This patchset makes it supported on all STM32 families by:
- moving spi_s structure at family level instead of board level
- using the F4 spi_api.c reference implementation and making it a common
stm_spi_api.c file which makes maintenance a lot easier.
- the only part that needs to be implemented for each family is the computation
of the clock frequency input to the spi peripheral which is not the same
accross families. So this is what remains in the spi_api.c of each family.
Because of the introduction of the common file, all the above modifications
needs to be done at once.
Laurent MEUNIER
Sam Grove
Martin Kojtal
Laurent MEUNIER