Commit Graph

4 Commits (fba139024133cfe86f2ca5bf2914e30e473e5bcc)

Author SHA1 Message Date
ohagendorf 883b2bc0ce [STM32xxx] CoIDE exporter and gcc_arm
- CoIDE options: wrap main and linker option DiscradUnusedSection=1 was
missing in some targets
- CoIDE options: corrected flash loader config for Nucleo_F030 and
Nucleo_F072
- CoIDE options: corrected memory layout (not used per default but now
it is the same as in linker script)
- gcc linker script: changed the memory size from hex number e.g. 0x2000
to decimal 8K
2014-12-07 20:07:56 +01:00
ohagendorf f11facdc63 [EXPORT][CoIDE] [DISCO_407] and [NUCLEO_F4x1] memory areas
The templates now contains the memory areas preconfigured as they are
used in linker scripts. When the CoIDE linker option 'Use memory layout
from memory window' is manually switch on the correct memory layout is
already there.
2014-09-28 14:49:57 +02:00
ohagendorf ee8d3461c4 [EXPORT][CoIDE] changed virtual directory names
changed the names of virtual directories to 'sources' and 'headers'
2014-09-27 01:10:42 +02:00
ohagendorf 703f8f9331 [EXPORT] [NUCLEO_F4x1RE] and [DISCO_F407VG] export to CoIDE
- export project with export_test.py
- projects can be compiled, downloaded and debugged with CoIDE 1.7.7
- STM32F411xx is not yet supported directly by CoIDE
- STM32F401RE it not supported but STM32F401RB is (differences in flash
size)
- but the generated project files for the Nucleo boards contain correct
FLASH and RAM sizes and that seems to be enough
2014-09-19 21:24:08 +02:00