5 Commits (eb60e67d92fa6d01b8e6a822434010a53d4eb006)

Author	SHA1	Message	Date
Kevin Bracey	1f94428a56	Update HAL CRC API ... * Change "is supported" check to be a macro, so it can be done at compile-time. * Eliminate weird shift on 7-bit CRCs. * Add support for 32-bit CRCs and reversals to TMPM3HQ.	2019-11-13 14:31:49 +02:00
Alexandre Bourdiol	adcf0e2fa5	DISCO_H747I Dualcore support ... Add 2 targets for DISCO_H747I dualcore: * DISCO_H747I -> for CM7 core * DISCO_H747I_CM4 -> for CM4 core Current restrictions: * TICKLESS deactivated * DeepSleep not supported (DeepSleep wrapped to sleep) Warning: use of the same IP (example I2C1) by both core at the same time is not prevented, but is strongly not recommended. Some Hardware Semaphore are use for common IP, to manage concurrent access by both cores: Flash, GPIO, RCC. Warning: Drag and drop of binary to DISCO_H747I will flash CM7. In order to flash CM4, one can use STM32 CubeProgrammer tool.	2019-10-14 18:02:57 +02:00
jeromecoutant	aa31b1268a	STM32H7 watchdog patch	2019-07-05 14:44:43 +02:00
Alexandre Bourdiol	a339084684	STM32: pwmout_write: configure channel only when not already enabled ... Fix PWM glitch on write(), TARGET_STM/pwmout_api.c, #10734	2019-06-20 17:49:16 +02:00
jeromecoutant	25e4316963	STM32H7 directory cleanup and refactoring	2019-06-06 10:48:11 +02:00