The sct file path generated in the online compiler
is incorrect. Fix that by changing the correct_scatter_shebang
API to accept a FileRef object instead and use the path.
This change should go with change in online compiler that removes
the override for correct_scatter_shebang.
The FileRefs allow you to preserve the correct file paths in the online
compiler. It also allows you to preserve the correct file paths for
generated files.
1. Override IlinkOverrideProgramEntryLabel and IlinkProgramEntryLabel to specify
entry point for debuger.
2. Refer to doc at the link below for post-export steps. Usually, 'export' is nearly
out of the box and just install 'Nu-Link Driver (IAR)' to update Nuvoton device
database in IAR.
https://github.com/OpenNuvoton/NuMaker-mbed-docs/blob/master/IAR/DEBUG_IAR.md
mbed_config.h is a file that is placed in your project root when you
export. This allows the configuration to be used by your IDE. When this
file already exists (due to a previous export), it changed the compiler
include option on Windows from "-include mbed_config.h" to "-include
.\mbed_config.h". The "\" character was interpreted as an escape
character "\m" and broke the build. This converts all resource paths to
use the Posix path separator "/" before writing project files to avoid
this issue.
The call to encode() was causing the include paths to be placed in the
uvision product file with the prefix "b'" and the postfix "'". This
broke the parsing of this file and broke the build.
In case of a non-overwriting change to an exported config file
the previous logic appended a new block of text to the previous file
every time the to-be-written block of text was not exactly matched.
This parses the old config file and the to-be-written changes into
sets, which can then be compared. If all of the incoming lines are
found in the old config file set, no changes are made. If some
incoming lines are not found in the old config file, only these are
appended.
Fixes#9974
The error was that the Asymmetric CPUs were assumed to have the same
structure as the Symmetric CPUs. This is clearly false.
This PR changes the FPU detection of Asymmetric CPUs to find the correct
core and use it's cpu settings.
[x] Fix
[ ] Refactor
[ ] Target update
[ ] Functionality change
[ ] Docs update
[ ] Test update
[ ] Breaking change
Added WiFi_Bt CM4 PSA target in mbedos json
Added SPE-NSPE mailbox initialization for CM4 SystemInit
Made similar to FUTURE_SEQUANA configurations
Copied FUTURE_SEQUANA CM0 SPM part for WiFi_Bt smoke test
Added CY8CKIT_062_WIFI_BT_M0 and CY8CKIT_062_WIFI_BT_M0_PSA targets
Sorted files for new CY8CKIT_062_WIFI_BT_M0 and CY8CKIT_062_WIFI_BT_M0_PSA targets
Copied files for CY8CKIT_062_WIFI_BT_M0_PSA from FUTURE_SEQUANA
Copied and updated cm0p start files
Corrected according to FUTURE_SEQUANA
Changes to M0 startup files to have SPM started
Fixed implicit declaration warning
Commented interrupts enabling according to FUTURE_SEQUANA flow
Updated prebuild spm_smore CM0 hex for CM4 target
Turned on greentea environment
Used special memory region for common CM0/CM4 data
Updated prebuild CM0 SPM hex
Placed shared memory region for flash operations into SPM shared memory region
Updated cyprotection code and configuration
Start address of protected regions is set by a defined number from target.json
Added masters pcMask configuration
Added support for PSA target to WIFI_BT board
Enabled resources protection for SPM
Aligned RAM usage according to Cypress FlashBoot and CyBootloader
alligned protection config
Added CYW943012P6EVB_01_M0 target
Enlarged heap size, remobed nv_seed
Added heap reservation in linker script from mbed-os
Removed heap size definition
turned on nv_seed config
Removed nv_seed macros
Enabled protection for PSoC6 CM0
Added PSoC6 CM0 PSA readme
Enabled mbed_hal-spm test
Enabled nv_seed and removed unneeded ipc config define
Added SPDX string to feature_ble cypress target files
Removed unneeded supported_toolchains lines for Cypress targets
Disabled protection settings
Corrected flash initialization for PSoC6 CM0 PSA
Changed PSoC6 IPC6 protection for flash
Enabled special flash initialization and enabled protection settings
Updated and added new prebuild PSoC6 CM0 PSA hex files
Disabled HW TRNG and CRC for PSoC6 CM4 PSA target
Added missing const to allow types to match
Updated PSoC6 WIFI_BT_PSA prebuilt directory
Moved PSoC6 shared section usage area definition to begin of ld
Added initial ARM_STD linker and startup files for PSoC6 CM0
Added initial IAR linker and startup files for PSoC6 CM0
Added defines to disable some SPM protection settings for PSoC64
Moved Flash function variables into separate memory region
Added defines for new Public area definition
Updated PSoC6 CM0_PSA hex-files
The Makefile is run from the build directory. The source files were
properly prefixed with "../", however the paths provided to the
assmebler were not. This ensures the assembler include paths are
prefixed properly.
Reference template file is used from IAR8.32 installation available at path
"Embedded Workbench 8.2\arm\config\template\ConvertToIAR\template_project.ewp"
Also added trustzone configs in iar_definitions.json
The approach for the hex_files subset selection is identical
to makefile exporter: https://github.com/ARMmbed/mbed-os/pull/9466
Single hex file should be passed to srec_cat when hex_filename
is set in targets.json or mbed_app.json.
Brian Daniels
Naveen Kaje
Laurent Meunier
Andrii Lishchynskyi
ccli8
jeromecoutant
studavekar
Jimmy Brisson
Artturi Ramanen
Mahesh Mahadevan
Oleg Kapshii
Martin Kojtal
Senthil Ramakrishnan
Cruz Monrreal
Deepika
kegilbert
Volodymyr Medvid