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1640 Commits (ddf5060ef923f929f3673f9fc542e0824c5fb61d)

Author SHA1 Message Date
Rob Vlaar e0c20d5294 fixed indentation 2019-02-08 16:50:27 +00:00
Rob Vlaar b4ca822f22 Reset internal vref buffer after an ADC conversion using the config channel function 2019-02-08 16:50:27 +00:00
jeromecoutant 4ba8e0e754 STM32: PeripheralPins files minor update 
Script version 1.4
CubeMX DB version DB.5.0.1
 2019-02-08 16:50:27 +00:00
jeromecoutant 2eec7c8562 STM32H7: 0S2 compilation 2019-02-08 16:50:27 +00:00
Fahim Alavi fad7ff9655 Fixed modem reset functionality to avoid low time to trigger module switch off 2019-02-08 16:50:27 +00:00
jeromecoutant 206589045c STM32L496xG: increase IAR heap size 2019-01-25 16:19:11 +00:00
jeromecoutant 235d3b88d7 STM32: FDCAN support for H7 family 2019-01-25 14:29:59 +00:00
kevin.ong 50e2e05442 stm32: fix indent style 2019-01-25 14:29:59 +00:00
kevin.ong f0006adb41 stm32: fix typo 2019-01-25 14:29:59 +00:00
kevin.ong 0e69cd95de stm32: fix some F0 target compile error 2019-01-25 14:29:59 +00:00
kevin.ong 56e488a2fd stm32: F1/F2/F4/L1 set to not supported HW CRC 
Currently, mbed supported input data format fix on bytes, so those
devices are not supported at default.
 2019-01-25 14:29:59 +00:00
kevin.ong 38e1152eea stm32: fix F1/F2/F4/L1 compile fail after enable CRC 
Those series have not CRC_POLYLENGTH_32B definition
 2019-01-25 14:29:59 +00:00
kevin.ong 536b7a645a stm32: remove empty line 2019-01-25 14:29:59 +00:00
kevin.ong 6688b55a58 stm32: Improve the CRC function to support fully accumulate 
Tested on DISCO_L476VG and NUCLEO_L476RG
 2019-01-25 14:29:59 +00:00
Fahim Alavi 7aa3f4855e PB_1 is not connected to D4 in R412M above 2019-01-25 14:29:59 +00:00
Fahim Alavi 19a88e0ddc Set target C030-R412M in mbed 2019-01-25 14:29:59 +00:00
jeromecoutant 3b4952124a STM32: replace missing #ifdef DEVICE_xxx 2019-01-14 13:06:14 +00:00
jeromecoutant 1fa1ea0743 STM32: astyle check 2019-01-14 13:06:14 +00:00
jeromecoutant 9d1d967587 STM32 : typo error in QSPI 2019-01-14 13:06:14 +00:00
kevin.ong 3c03d708bb STM32L476VG: fix wrong pin map function on ADC channels 
This issue is start on https://github.com/ARMmbed/mbed-os/pull/6931

ADC pins must need STM_PIN_ANALOG_CONTROL_BIT to call LL_GPIO_EnablePinAnalogControl
 2019-01-14 13:06:14 +00:00
jeromecoutant 84a0a5d550 STM32 L0 & L1: FLASH is EEPROM 2019-01-14 13:06:14 +00:00
Alastair D'Silva b0220082de Don't use define checks on DEVICE_FOO macros (partner code) 
The DEVICE_FOO macros are always defined (either 0 or 1).

This patch replaces any instances of a define check on a DEVICE_FOO
macro with value test instead.

Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
 2019-01-14 13:06:14 +00:00
jeromecoutant 5598112863 STM32L4 ADC VBAT CHANNEL 2019-01-14 13:06:14 +00:00
Wilfried Chauveau d08c64eac3 add bootloader support to the DISCO_F469NI 2019-01-14 13:06:14 +00:00
bcostm 2dfd1e5466 NUCLEO_H743ZI: add crash reporting for IAR 2019-01-14 13:06:14 +00:00
bcostm c6f3d9244a NUCLEO_H743ZI: include rtc LL driver 2019-01-14 13:06:14 +00:00
jeromecoutant 1b67295203 NUCLEO_H743ZI: add initial SDK 2019-01-14 13:06:14 +00:00
jeromecoutant 53ff2d5d05 STM32L0 ADC TEMPERATURE CHANNEL rework 2019-01-14 13:06:14 +00:00
Kevin Bracey 2e3776487e Revert "STM32 RTC : skip rtc_write if possible" 
`rtc_write` must start the RTC. `time()` uses `rtc_write(0)` to start
the RTC if it is not already enabled, but this check made that not
work.

There's no point trying to optimise this case in a HAL - if we wanted
`set_time()` to protect against users making pointless adjustments, the
implementation should be there. But even then, you might want different
levels of hysteresis depending on application, so it's probably best
left to applications.

This reverts commit 9da5e48941.
 2018-12-27 22:26:04 -06:00
Ashok Rao a332a90586 MTB_ODIN_v2_fixes 
1. Removed redundant code comments. Added relevant ones for MTB pins.
2. More SPI_CS pins added for peripherals on the MTB.
3. Disabled LSE_Clock as it is not present on the MTB in targets.json
 2018-12-27 22:26:04 -06:00
jeromecoutant e06b7863cc STM32F429/STM32F439 alignment 2018-12-27 22:26:04 -06:00
mudassar-ublox 2a5e2a7a0d Ublox C030 ADC internal channels added 2018-12-27 22:26:04 -06:00
jeromecoutant 355807cedf STM32 LPTICKER with RTC : optimise sleep duration 2018-12-27 22:26:03 -06:00
jeromecoutant f5577c005e STM32 RTC : skip rtc_write if possible 2018-12-27 22:26:03 -06:00
Laurent Louf 45e7296e05 Add some rounding to determine the pulse value for PWM for the STM target. 2018-12-27 22:26:01 -06:00
jeromecoutant 0c4d7d4dd6 STM32L4 QSPI: correct register address 2018-12-27 22:26:01 -06:00
jeromecoutant ac0fb3cea0 STM32 QSPI: remove QUADSPI_BK2 as dual bank feature is not supported 2018-12-27 22:26:01 -06:00
jeromecoutant 5a27a9a699 STM32 QSPI: frequency calculation update 2018-12-27 22:26:01 -06:00
jeromecoutant 41cd8b3d10 STM32L496 : add QSPI definition 2018-12-27 22:26:01 -06:00
jeromecoutant c0ad4621e0 STM32F769 : add QSPI definition 2018-12-27 22:26:00 -06:00
jeromecoutant 356d5756ea NUCLEO_F746ZG : no embedded QSPI 2018-12-27 22:26:00 -06:00
jeromecoutant 018f72d6e4 STM32 : removed unused QSPI pin names 2018-12-27 22:26:00 -06:00
test user b6c98a99a9 ublox c030 pinName updated 2018-12-27 22:26:00 -06:00
jeromecoutant 23b25465bc STM32L4: correct RNG clock source 2018-12-27 22:25:59 -06:00
jeromecoutant c154da4123 STM32 LPTIM update for easy maintenance 2018-12-27 22:25:58 -06:00
jeromecoutant 2a65eacac3 STM32 mbed_sdk_init update for easy maintenance 2018-12-27 22:25:58 -06:00
jeromecoutant eb75ac95c9 STM32 SLEEP update for easy maintenance 2018-12-27 22:25:58 -06:00
jeromecoutant dc47e708b6 STM32 RTC update for easy maintenance 2018-12-27 22:25:58 -06:00
bcostm 6ff271b322 STM32L4 TRNG:Remove trng clock setting for L4 devices 
This will be done in the system_clock.c file instead.
 2018-12-27 22:25:58 -06:00
jeromecoutant 8d89854589 STM32 readme md file 2018-12-27 22:25:54 -06:00