* Make mbed_error use bitwise MbedCRC call rather than local
implementation.
* Remove use of POLY_32BIT_REV_ANSI from LittleFS.
* Move some MbedCRC instances closer to use - construction cost is
trivial, and visibility aids compiler optimisation.
* Make mbed_error use bitwise MbedCRC call rather than local
implementation.
* Remove use of POLY_32BIT_REV_ANSI from LittleFS.
* Move some MbedCRC instances closer to use - construction cost is
trivial, and visibility aids compiler optimisation.
4-byte addressing has been seen to cause failures on NORDIC
boards and with Macronix memories. Suppress the attempt to enable it
on that hardware (via vendor quirks and a target check) until either
the failure cause can be fixed or a more robust suppression mechanism
is implemented.
Use a vendor id check to only perform this enable on devices which define the
second configuration register where the fast mode enable bit lives.
Change _enable_fast_mode to use the standard status register reading and writing functions
Default to 2 status registers, but update this value if necessary
during vendor quirk handling for parts (currently only Macronix)
which have one status register and two control registers. For the
purposes of QSPIFBlockDevice, these are all considered status
(or at least "status-like") registers because they are all written
via the Write Status Register instruction.
Set the custom RDCR instruction for Macronix during quirk handling.
Update reading and writing of status registers to handle a variable
number of status registers.
Introduce a separate function for handling alterations to device interaction
which are not covered by the SFDP tables and therefore require checking against
the vendor id.
QSPIFBlockDevice::_clear_block_protection() has logic to retain the
WIP and WEL bits in status register 1, but it failed to account for
the situation where the QE bit is also in status register 1.
In _sfdp_set_quad_enabled, note the status register and bit therein
for the quad enable, so that _clear_block_protection can retain it.
This function writes a "config" register to ensure that the flash part
is in high performance mode, not low-power mode. This is required at
by at least MX25R6435F in order to operate at frequencies > 33MHz
(for reference, DISCO_L475VG_IOT01A runs the QSPI interface at 80 MHz).
The config register that this writes does not appear to be covered by
the SFDP spec (JESD216D.01) so this remains the status quo of
unconditional execution, as has been done on master since #8352.
* Refactor some headers to use relative path from Mbed OS root.
* Refactor some data types to compile on 64bit machines.
* Refactor some debug traces to use mbed_trace.
Encourage the usage of consistent types (there are currently
a mix of `int` and `unsigned int` used for qspi instructions)
QSPI commands are limited to 8 bits, to this is a typdef to char
Update to follow the same `goto exit_point` pattern that is used
by the rest of the functions to avoid leaving the mutex locked
when errors are detected and require the function to abort.
Propagate separate alt cycle and dummy cycle counts from QSPIFBlockDevice
down to the qspi driver, so that drivers which handle the two separately have
enough information to do so.
The QSPI spec allows alt to be any size that is a multiple of the
number of data lines. For example, Micron's N25Q128A uses only a
single alt cycle for all read modes (1, 2, or 4 bits depending on
how many data lines are in use).
All current PSoC 6 targets support the same QSPI frequency and minimum
program size. So specify a single entry rather than duplicating for
each device.
Reimplement atomic code in inline assembly. This can improve
optimisation, and avoids potential architectural problems with using
LDREX/STREX intrinsics.
API further extended:
* Bitwise operations (fetch_and/fetch_or/fetch_xor)
* fetch_add and fetch_sub (like incr/decr, but returning old value -
aligning with C++11)
* compare_exchange_weak
* Explicit memory order specification
* Basic freestanding template overloads for C++
This gives our existing C implementation essentially all the functionality
needed by C++11.
An actual Atomic<T> template based upon these C functions could follow.
Due to discovery of inconsistent sector sizes in devices storage the is_valid_erase function was adjusted,
For FlashIAPBD the 'code size' was included to the calculation, preventing faulty "virtual" addresses calculation.
For SlicingBD the same error was fixed and in all 3 validation functions that sent addresses for validation and program/read/erase
different addresses.
SPIFBlockDevice was using SingletonPtr without an include,
and only getting it via SPI.h.
Spotted while changing SPI to not use SingletonPtr - now
abandoned, but still this shouldn't have been relying on it.
Random number generation in case of IAR 8, requires TLS support.
Thread local storage is not part of Mbed OS, test is updated to have random
numbers sparse, but in future random number creation should be moved to main
thread, or use some other logic for randomization instead of rand() call.
The addresses dont have to change each run, just be unique.
Because address seeds repeat themselves each run, rand() will
produce repeating results that should not collide between
different threads.
Przemyslaw Stekiel
Kevin Bracey
Martin Kojtal
Kyle Kearney
Matthew Macovsky
RAJKUMAR KANAGARAJ
Seppo Takalo
toyowata
jeromecoutant
Anna Bridge
Maciej Bocianski
Ben Cooke
Veijo Pesonen
Michal Paszta
Pavel Slama
int_szyk
Lin Gao
Christopher Haster
Marten Lootsma
Qinghao Shi
Marten Lootsma
Chris Snow
Ryan Morse
David Saada
Offir Kochalsky
jk
Ari Parkkila
Amir Cohen
Deepika