Prevent mismatch between _owner and peripheral configuration. In the previous
implementation, the following code would leave the peripheral in an inconsistent
state:
```
SPI spi1(...); // _owner is NULL, peripheral config is 1
spi1.transfer(...); // _owner is 1, config is 1
SPI spi2(...); // _owner is 1, config is 2
spi1.transfer(...) // 1 thinks it still owns peripheral, doesn't reconfigure
```
This patch adds BLE Cordio support into MBED HAL. It contains:
* Cordio and TRIM object files
* The Cordio stack header file
* The Cordio library for Beetle Systems precompiled for GCC and ARMCC
The BLE implementation will be provided in a future patch in the mbed-os
repository.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
In Beetle systems eFlash and Cache Flash are always enabled by default.
This patch updates the Mbed SDK Init procedure to reflect the changes in
the eFlash and Cache Flash Drivers provided in a previous patch.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
This patch adds BLE Cordio support into CMSIS. It provides:
* A modification for the linker scripts for both ARMCC and GCC
compilers that adds the cordio specific sections.
* A method to access the Flash stored MAC Address.
The CORDIO_RO_2.1.o and TRIM_2.1.o objects that rappresent the Cordio
firmware will be added by a future patch.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
In Beetle systems eFlash and Cache Flash are always enabled by default.
This patch refines the interface of these drivers to match the
functionalities exposed by the platform.
This patch renames also writel/readl in these drivers to uppercase to follow
acros code convention.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
and update the using functions accordingly.
Usage:
bool interrupts_enabled = are_interrupts_enabled()
Remove superfluos shift in are_interrupts_enabled().
than an integer. This removes the need for all users to mask the returned
value with 0x1 to determine interrupt status.
Expose this function externally to allow other users to check interrupt
status in a manner which will work for both cortex-A and cortex-M .
Usage:
bool disabled = get_interrupts_disabled();
- changing device.h -> targets.json after rebase
- adding startup and config files for ARM_STD toolchain
- changing all STM32F7xx targets to ARM as default toolchain (instead of uARM before)
- nrf headers synchronized with the one in BLE implementation. This is a
short term fix. The nordic branches use a single nrf SDK and does not
have duplicate headers. Once this branch will be integrated, there will
be no more issues around duplicate headers.
- enable feature BLE in the targets.json. This fix was done a long time
ago in the nordic branch. Without it, it is not possible to compile BLE
examples.
Issue #2074
Assuming that OverSampling is initialized, the baudrate is now correctly
computed inside CMSIS (STM32 HAL) layer. This was not the case before but
most probably was fixed during latest L0 cube firmware upgrade:
commit ce436d5107
Author: svastm <simon.vanson@st.com>
Date: Thu Apr 14 14:39:53 2016 +0200
Update STM32CUBE_L0 from v1.2 to v1.5
We added "IPV4" of Compile Macro in "targets.json" file.
We failed in the reletion test of IPV4 because "IPV4" was not entered into our Build Target setting.
- __heap_size__ was used to allocate a fixed size region for the heap in
RW_IRAM1
- __user_setup_stackheap in sys.cpp uses Image$$RW_IRAM1$$ZI$$Limit as the
start of the heap, which leaves the fixed size region unused
Update of STM32L4 family CPI clock selection algo.
Maximum SPI clock is obtained from APB domain clock (based on HAL API).
Then algo sets maximum frequency available below requested frequency
Update of STM32L1 family CPI clock selection algo.
Maximum SPI clock is obtained from APB domain clock (based on HAL API).
Then algo sets maximum frequency available below requested frequency
Update of STM32L0 family CPI clock selection algo.
Maximum SPI clock is obtained from APB domain clock (based on HAL API).
Then algo sets maximum frequency available below requested frequency
Update of STM32F7 family CPI clock selection algo.
Maximum SPI clock is obtained from APB domain clock (based on HAL API).
Then algo sets maximum frequency available below requested frequency
Update of STM32F3 family CPI clock selection algo.
Maximum SPI clock is obtained from APB domain clock (based on HAL API).
Then algo sets maximum frequency available below requested frequency
Signed-off-by: Erwan GOURIOU <frq07517@st.com>
Update of STM32F1 family CPI clock selection algo.
Maximum SPI clock is obtained from APB domain clock (based on HAL API).
Then algo sets maximum frequency available below requested frequency
Update of STM32F0 family CPI clock selection algo.
Maximum SPI clock is obtained from APB domain clock (based on HAL API).
Then algo sets maximum frequency available below requested frequency
Update of STM32F4 family CPI clock selection algo.
Maximum SPI clock is obtained from APB domain clock (based on HAL API).
Then algo sets maximum frequency available below requested frequency
Introducing ADC2 support for NUCLEO_F446ZE implies to have the support
in the core part for all F4 chipsets that possibly support it (even if
not supported on all boards).
stdin converts the following character sequences:
\n -> \n
\r\n -> \n
\r -> \n
\n\r -> \n
For original behaviour, a serial object can be instantiated explicitly
stdout converts the following character sequences:
\n -> \r\n
\r\n -> \r\n
\r -> \r
\n\r -> \n\r
For original behaviour, a serial object can be instantiated explicitly
This is a hack to get debug builds applications that use uVisor to work.
The assertions in core_util_critical_section fail because interrupts can't
actually be disabled from unprivileged mode.
Without this hack, core_util_critical_section_enter() calls
mbed_assert_internal() when the assertion fails, which calls
core_util_critical_section_enter() again, which calls
mbed_assert_internal() again; this is infinite recursion.
core_util_critical_section_enter needs some fixing.
If you don't specify the start address of a section explicitly, that
section can end up at different addresses depending on its alignment. If
the alignment of a section is not explicitly set, it inherits it from
the element with the highest alignment inside that section.
Since the uVisor code is in the .text section, and it *must* end up at a
known location, we set the start address of .text to 0x410, which is the
value that the uVisor binary expects.
This patch enables RTOS support on Beetle.
It contains:
* Updated Beetle Startup code for ARMCC
* Modified SysTick Driver
* RTOS specific configuration parameters
* RTOS specific test suite enablement
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
The malloc lock functions were not declared as extern "C" so they
are not getting linked to the standard library. Add extern "C" to
fix this.
This bug was introduced in the commit:
d0b7b3b497 -
Fix duplicate symbols for malloc lock and unlock
The current version of MBED test environment requires LEDs to be present
in the platform.
Beetle HW does not provide any user programmable LEDs. This patch provides an
emulation of the feature by using dummy PINs.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
This patch adds support for BEETLE SoC Target into the HAL layer.
It contains:
* Beetle Platform Configuration
* I2C API
* SPI API
* Serial API
* Port API
* us Ticker API
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
This patch adds support for BEETLE SoC Target into the CMSIS layer.
It contains:
* Beetle System Core
* APB DualTimer Driver
* APB Timer Driver
* eFlash Driver
* Flash Cache Driver
* ARM Toolchain Support
* GCC ARM Toolchain Support
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
This patch adds support for the BEETLE Target. The compilers supported by
this target are:
* ARMCC
* GCC ARM
The exporters and the CMSIS/HAL components will follow in future patches.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
This fix is a solution for issue #816 when having two separate IRQ handlers
in Timers (UPDATE Irq and OutputCompare Irq). The update priority needs to
be higher to avoid undefined behaviours.
Change-Id: Ic143ed0f3e4e42ad5f7b95337d8c005b7ec61274
This fix is a solution for issue #816 when having two separate IRQ handlers
in Timers (UPDATE Irq and OutputCompare Irq). The update priority needs to
be higher to avoid undefined behaviours.
Change-Id: I5ef2c27926167ed22108901cd63586692a5f8f90
This is a partial revert of 07b841b and currently we are only reverting the
STM32F0xx family because new fix will be presented that's why we want to keep,
still the original solution only F1xx family (it will be fixed in future).
Change-Id: I147065299310c9fea499bf3ced8808a44699a1a1
Add a virtual destructor to classes which have a virtual lock and
unlock. Remove the virtual qualifier from functions in
InterruptManager since this class cannot be extended.
When the malloc lock and unlock functions are inside a library they
conflict with the standard libraries weak version of these functions.
This is because of the way weak references are handled by the linker.
This patch renames the lock and unlock functions defined inside RTX
so they do not conflict. A thunk inside retarget.cpp then calls the
RTX functions. This problem does not occur with retarget.cpp since
it is always build into an object file rather than a library file.
This is backwards-compatible with unsupported targets.
If an application is compiled using the K64F target without uVisor
(UVISOR_PRESENT not set or set to 0) then uvisor_init() will just be an
empty function that immediately returns.
Aksel Skauge Mellbye
Michel Jaouen
Vincenzo Frascino
Martin Kojtal
adustm
Olaf Hagendorf
svastm
Anna Bridge
Vincent Coubard
Laurent MEUNIER
Jarek Zgoda
Sam Grove
tomoyuki yamanaka
Christopher Haster
Mahadevan Mahesh
Colin Hogben
Erwan GOURIOU
Mike Fiore
Rohit Grover
Laurent MEUNIER
Simon Hughes
Bogdan Marinescu
Bartosz Szczepanski
Alessandro Angelino
Bogdan Marinescu
Jaeden Amero
Niklas Hauser
Brian Daniels
Russ Butler
Andrii Anpilogov
Maciej Bojczuk