Commit Graph

90 Commits (bc098d027207b1c7e15c8bf8175e5afb15492f76)

Author SHA1 Message Date
Volodymyr Medvid 534becb175 PSOC6: correctly align hex files with split text sections
When the original PSOC6 CM4 hex file contains unalinged text sections
that span through multiple intelhex segments, aligned segments (filled
with zeroes) overlap with the original data segments, resulting in
error thrown by ihex.merge(alignments, overlap='error').
Such hex file can be produced when the ELF is built with ARM MDK Compiler
with --split_sections option:
http://www.keil.com/support/man/docs/armcc/armcc_chr1359124944914.htm

Change the merge strategy to overlap='ignore', so that the overlapping
zero-filled segments are skipped.
2019-02-20 22:34:10 +02:00
Cruz Monrreal II 8c10cb0b8d Prefixed string to properly be parsed as bytes 2019-02-12 12:05:28 -06:00
Aleksi Klasila 3e88cf7e83 REALTEK_RTL8195AM daplink timestamp from os.environ 2019-02-11 18:11:07 +02:00
Cruz Monrreal c9e00cf781
Merge pull request #9480 from deepikabhavnani/core_arch_v8m
Refactor core optional parameters (FPU + DSP + Security extensions)
2019-01-31 10:22:09 -06:00
Martin Kojtal 9265c19e2e
Merge pull request #9394 from jeromecoutant/PR_PERIPH
STM32: PeripheralPins files update from lastest CubeMX tool version
2019-01-31 11:21:09 +01:00
Cruz Monrreal e965aa6640
Merge pull request #9509 from vmedcy/psoc6-daplink-hex
PSOC6.py: generate hex files with 16 bytes per row
2019-01-28 10:38:15 -06:00
Volodymyr Medvid 5c384f10e7 PSOC6.py: generate hex files with 16 bytes per row
DAPLink implementation on Cypress kits cannot handle hex files
with 64 bytes per row: refer to https://github.com/ARMmbed/DAPLink,
source/daplink/drag-n-drop/intelhex.c, hex_line_t struct, data field.
2019-01-25 10:07:00 -08:00
deepikabhavnani f7d49fdc82 Change DSP variant symbol to `E` from `D`(d-double floating point) 2019-01-25 09:31:44 -06:00
jeromecoutant 16028e3796 STM32_gen_PeripheralPins.py v1.5
Use dedicated PinMap for each QSPI data line #9438
2019-01-24 11:00:00 +01:00
jeromecoutant bdc91b0a9a STM32_gen_PeripheralPins.py v1.4
Minor updates:
- remove QSPI BK2
- beautifier edition
- use STM_MODE_ANALOG_ADC_CONTROL for L4 family
2019-01-24 10:25:36 +01:00
Volodymyr Medvid a48ee113ea PSOC6: refactor M0 image merging, enable export to makefile
Rename the existing PSoC-specific m0_core_img key in targets.json
as a more generic hex_filename key. Update makefile exporter to select
the subset of resources.hex_files matching the hex_filename value.
Without this fix, multiple prebuilt CM0+ hex files are found in the
target resources and erroneously passed to the srec_cat tool.

The fix is generic so other targets that need post-build hex merging
can use this key to pass the correct image to srecord tool.

The fix also removes sub_target key: instead, rely hex_filename json
key to detect if the hex image merging needs to be done.
The sub_target is not used in mbed-os codebase for anything else.

It is possible to override the hex file name in mbed_app.json:
{
  "target_overrides": {
    "*": {
      "target.hex_filename": "my_custom_m0_image.hex"
    }
}
2019-01-22 15:40:22 -08:00
Volodymyr Medvid 5b0daadd18 PSOC6.py: do not require metadata during HEX merging
Replace hard-coded numeric offsets of PSoC 6 hex file sections
with sensible constants.
Do not attempt to update the checksum and metadata contents
if the sections are not found in the original HEX file.
2019-01-22 15:40:22 -08:00
Volodymyr Medvid 226edc1abd PSOC6.py: remove silicon ID check
PSoC 6 hex files contain 4-byte chip ID at virtual offset 0x90500002
added by PSoC Creator or cymcuelftool from .cymeta ELF section.
merge_images compares chip ID in CM0+ and CM4 hex files and raises
an exception in case of mismatch. Chip ID is different for each MPN
(for example, 0xE2072100 for CY8C6347BZI-BLD53 and 0xE2062100 for
CY8C6247BZI-D54). CM0+ prebuilt images target CY8C6347BZI-BLD53
but should be compatible with other PSoC6 MPNs.
Remove the check to enable merging CM0+ images with CM4 applications
built for different MPNs, with empty or absent cymetadata.
2019-01-22 15:40:22 -08:00
Alastair D'Silva aa80b7c70a Don't use define checks on DEVICE_FOO macros (partner code)
The DEVICE_FOO macros are always defined (either 0 or 1).

This patch replaces any instances of a define check on a DEVICE_FOO
macro with value test instead.

Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
2018-12-20 20:02:29 +11:00
deepikabhavnani f05e7b77d0 Add core option for Cortex-M33 with DSP enabled
Signed-off-by: Deepika Bhavnani <Deepika.Bhavnani@arm.com>
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2018-12-07 12:20:01 -06:00
Oren Cohen 2e19868ff9 Prepare postbuild for prebuilt images 2018-12-06 09:35:50 +02:00
Oren Cohen f1d3eb9340 Add FUTURE_SEQUANA_PSA target
* Modify linker scripts to be compatible with bootloader and PSA
* Add memory protection
* Modify original post-build step to allow link with PSA binaries
* Config kvstore for ITS on FUTURE_SEQUANA_PSA
* Enable PSA-Crypto on PSoC6 with NVSeed
2018-12-04 18:38:50 +02:00
Martin Kojtal b0054897b1
Merge pull request #8854 from AdamZhang0124/realtek-rtl8195am-SMCC_FOTA-bin_file_name-update
SMCC FOTA: bin name change
2018-12-03 13:23:53 +01:00
Oren Cohen dd73fa689c PSA SPM
* Intorduce PSA-SPM to mbed-os
* Add SPM tests (for PSA targets)
* Add PSA PRoT internal storage Secure implementation
* Integrate SPM into the boot proccess
* PSA manifest data generator
* Introduce PSA targets skeleton to mbed-os
* Add artifact delivery to the tools
2018-11-27 09:16:35 +02:00
Lu 3f7b235782 This PR modifies the name of the bin file generated for SMCC FOTA feature
This PR modifies the name of the bin file generated for SMCC FOTA feature

Description
Modify name of the bin file from '-payload.bin' to '_update.bin' in REALTEK_RTL8195AM.py file to adapt the manifest tool requirment for the SMCC FOTA feature.

Pull request type
[ ] Fix
[ ] Refactor
[x] Target update
[ ] Functionality change
[ ] Docs update
[ ] Test update
[ ] Breaking change
2018-11-23 21:00:46 +08:00
jeromecoutant 1ea28973b2 TOOLS : Add missing M33 and M33F in python scripts 2018-11-05 17:44:15 +01:00
Leszek Rusinowicz 7d322dcd41 Simplified M0/M4 binary merging functionality. Now, M0 binary image to be used has to be explicitely named in a json file (can be ovverriden in mbed_app.json).
Exporter hooks removed completely.
Cleanup and improvements to the comments, including removal of the redundant doxygen comments.
Code run through astyle. Additionally:
 - changes to drivers/Timer.cpp reverted
 - ipcpipe_transport.* files removed as they are not used for now,
 - fixed condition in stdio_init.cpp to perform serial initialization only when STDIO is enabled,
 - added missing resurce manager call in PWM initialization,
 - us_ticker initialization changed to use pre-reserved clock divider (to avoid resource manager call).
Changed reporting level from info to debug in PSOC6.py.
Added missing includes for function declarations in startup files.
Fixed (removed) garbadge text in psoc6_utils.c
Precompiled binaries updated for recent changes in psoc6_utils.c and moved to a separate folder; README and LICENSE files added.
2018-11-01 22:14:06 +01:00
Leszek Rusinowicz 9b1db83eaa Added required changes outside of TARGET_Cypress tree:
1. In drivers/Timer.cpp make sure that hardware timer is initialized outside of critical section.
   This is because on PSoC 6 hardware resources are shared between both cores
   and we have to make sure that the other core is not already using a particular resource.
   This mechanism is based on interprocessor communication taht cannot be handled iside of
   critical section.
2. Added support for post-binary hook function for PSoC 6 targets, so the hex image for M0+ CPU core
   can be merged with M4 core image for the final image.
3. Added possibility to use hook function from exportes, so the M0+ hex image could be included
   in the generated project.
4. Included hex images in the build dependency list, so the update of image is catched by the
   build process.
2018-11-01 20:19:21 +01:00
Jimmy Brisson 9c3307ab20 tools: Raise NotSupported when target definition is incomplete
### Description

Noticed by the online compiler:
When a user has an incomplete target definition, the error is not show
to the user. That's because it's reported as a `KeyError`. This PR adds
an outer `NotSupportedException` so that the outer catch statement knows
that this is not a build system crash, but a user error.

### Pull request type

    [x] Fix
    [ ] Refactor
    [ ] Target update
    [ ] Functionality change
    [ ] Breaking change
2018-10-17 18:00:57 -05:00
Cruz Monrreal 5102610f11
Merge pull request #8275 from theotherjimmy/online-nrf51-upstream
tools, NRF51-post-build: Use paths to hex files
2018-10-08 10:21:03 -05:00
Jimmy Brisson 080c72bb47 tools, NRF51-post-build: Use paths to hex files
### Description

The NRF51 post build hook finds it's hex files using the Resources
object. This PR fixes the corner case where the hex files within a
project have a name!=path (This really only happens online).

### Pull request type

    [x] Fix
    [ ] Refactor
    [ ] Target update
    [ ] Functionality change
    [ ] Breaking change
2018-09-27 14:44:19 -05:00
Russ Butler ab50681c33 Rename device option STCLK_OFF_DURING_SLEEP
Rename STCLK_OFF_DURING_SLEEP to SYSTICK_CLK_OFF_DURING_SLEEP to avoid
confusion with the STmicroelectronics.
2018-09-12 14:40:25 -05:00
Cruz Monrreal 2e081dc7d0
Merge pull request #7644 from theotherjimmy/components
Tools: Scan for "components"
2018-08-28 17:55:01 -05:00
Jimmy Brisson 4ef12ccdbc Culumative attirbutes always exist 2018-08-27 11:12:02 -05:00
Jimmy Brisson 79ee1b8e02 Add "components" 2018-08-27 11:12:01 -05:00
Cruz Monrreal 2f8e679183
Merge pull request #7592 from orenc17/remove_uvisor
Remove uVisor from mbed-os
2018-08-25 19:52:24 -05:00
Oren Cohen 787317b7eb Remove uVisor from mbed-os 2018-08-22 16:36:59 +03:00
jeromecoutant 43258a8ff4 STM32 : add all QSPI pins in available targets 2018-08-22 15:02:08 +02:00
Jimmy Brisson ae033da12f Use mapping of core->arch ver. for tc picking 2018-07-19 10:55:35 -05:00
Jimmy Brisson 4400765ece Add `Mxx_NS` core-based labels 2018-07-12 18:01:37 +08:00
Jimmy Brisson 4e6b830c91 Allow hex BL, SD and application merging 2018-06-19 09:27:09 -05:00
Martin Kojtal eb3d3fdb54
Merge pull request #6929 from jeromecoutant/PR_SCRIPT
STM32 : script to generate PeripheralPins.c for new target addition
2018-06-19 14:26:22 +02:00
jeromecoutant 5fba2e49c5 STM32_gen_PeripheralPins.py : Add license header 2018-06-12 14:30:54 +02:00
Bartek Szatkowski 6e9f04bf2f Rename DEVICE_LOWPOWERTIMER to DEVICE_LPTICKER
That's to match DEVICE_USTICKER.
2018-05-25 12:20:09 -05:00
jeromecoutant 5b43961860 STM32: move STM32_gen_PeripheralPins.py to tools/targets 2018-05-21 17:22:19 +02:00
Jimmy Brisson 542bcebac7 Use notify API in post-build scripts 2018-04-27 14:46:35 -05:00
Jimmy Brisson a0b305b351 Use pyelftools for Realtek post-build script 2018-04-16 09:06:38 -05:00
Jimmy Brisson a9e3a4fa28 Correct Realtek post-build script to work in the online compiler 2018-03-16 10:09:03 -05:00
Jimmy Brisson cca4425af6 Python2+3: iteritems -> items 2018-02-05 11:04:36 -06:00
Jimmy Brisson 380ecb1b0e Python2+3: working through many has_attr exceptions 2018-02-05 11:04:01 -06:00
Jimmy Brisson 68737f2762 Python2+3: Things import 2018-02-05 11:03:44 -06:00
Cruz Monrreal 9a47f09ea9
Merge pull request #5910 from OSHChip/typo-fix
fix typos in lint.py
2018-01-26 10:36:33 -06:00
drewcassidy 6f9aa07491
fix typos in lint.py 2018-01-23 19:19:43 -08:00
Cruz Monrreal 47a128a5e5
Merge pull request #5882 from ashok-rao/br-MTB_Dragonfly
Add MTB MTS_Dragonfly as a new target.
2018-01-19 13:58:03 -06:00
Ashok Rao 9ee69854ff Adding MTB MTS_Dragonfly as a new target 2018-01-18 17:08:59 +00:00