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2064 Commits (b9d824d67cb15cf43a205aa5c78336aaa2aaeecf)

Author SHA1 Message Date
Kyle Kearney 6b1a21b7f0 Update STM driver changes for clarity 
- Use a switch statement rather than shifting and masking to compute
  the AlternateBytes value.
- Rename rounded_size to alt_bytes to clarify its purpose.
 2019-11-18 15:42:08 +00:00
toyowata 9ab22274a6 Add bootloader support for Seeed Arch-MAX 2019-11-18 15:42:08 +00:00
Laurent Meunier d92adcd28c Clearing UART TC Flag prevents deep sleep, so do not clear it 
The TC flag is used in function serial_is_tx_ongoing to check if there is
an ongoing serial transmission. So this Flag must not be cleared at the
end of the transmission, otherwise, serial_is_tx_ongoing will notify that
TX is ongoing.

The impact is that it may prevent deep sleep to be entered.

Also there is no need to clear this flag at the end of the transaction
because it will be cleared automatically by HW when a new transmission
starts.
 2019-11-18 15:42:08 +00:00
Alexandre Bourdiol 1e351720a7 Mbed patch of STM32cube for bootloader: use NVIC_FLASH_VECTOR_ADDRESS 2019-11-18 15:42:08 +00:00
Alexandre Bourdiol bdb0082bc9 Update HAL/LL EXTI to have default API applied on current core and nott CPU1 2019-11-18 15:42:08 +00:00
Alexandre Bourdiol 7846c9fe91 SystemCoreClock should correspond to current core clock and not D1 clock. 2019-11-18 15:42:08 +00:00
Alexandre Bourdiol 5418d70813 DISCO_H747I Dualcore support 
Add 2 targets for DISCO_H747I dualcore:
* DISCO_H747I      -> for CM7 core
* DISCO_H747I_CM4  -> for CM4 core

Current restrictions:
* TICKLESS deactivated
* DeepSleep not supported (DeepSleep wrapped to sleep)

Warning: use of the same IP (example I2C1) by both core at the same time is not prevented,
but is strongly not recommended.
Some Hardware Semaphore are use for common IP, to manage concurrent access by both cores: Flash, GPIO, RCC.

Warning: Drag and drop of binary to DISCO_H747I will flash CM7.
         In order to flash CM4, one can use STM32 CubeProgrammer tool.
 2019-11-18 15:42:08 +00:00
Janne Kiiskila 67fbe49819 stm32f4xx_hal_pcd.c@346,22: unused variable 'ep' 
Compiler warning fix, trivial. One function has an unused
variable, delete that line.
 2019-11-18 15:42:08 +00:00
adbridge 070269295f Add OKDO platform 
Manually ported from PR11407
 2019-10-16 12:10:38 +01:00
jeromecoutant 19b641bb66 STM32L151: update calibration memory address 2019-10-16 11:58:32 +01:00
jeromecoutant 82f2b72777 DISCO_L4R9I: update default STMOD+ pin 2019-10-16 11:58:32 +01:00
Kyle Kearney 65e726eb9e Fix possible negative QSPI alt count on STM 
Remove an extraneous decrement operation in cases where the alt
bits size is a multiple of 8.
 2019-10-16 11:58:32 +01:00
Matthew Macovsky 08a2709993 Allow for arbitrary QSPI alt sizes 
The QSPI spec allows alt to be any size that is a multiple of the
number of data lines. For example, Micron's N25Q128A uses only a
single alt cycle for all read modes (1, 2, or 4 bits depending on
how many data lines are in use).
 2019-10-16 11:58:32 +01:00
Ben Cooke 9145b72433 Add MTS_DRAGONFLY_F413RH platform to mbed-os 2019-10-16 11:58:32 +01:00
jeromecoutant b2e0a13730 STM32H7 ST CUBE V1.5.0 update 2019-10-16 11:53:52 +01:00
Vincent Veron 85757ce198 STM32H7 : use RAM instead of DTCMRAM (GCC_ARM toolchain) 2019-10-16 11:53:52 +01:00
Vincent Veron 7561e770a3 STM32H7 : use RAM instead of DTCMRAM (ARM toolchain) 2019-10-16 11:53:52 +01:00
Vincent Veron dd9f9e1cb5 STM32H7 : use RAM instead of DTCMRAM (IAR toolchain) 
Keep vector table and crash data ram in 0x20000000 for
tests-mbed_platform-crash_reporting test.
Move the rest in RAM (0x24000000). This is needed for ethernet and allows
user to use more RAM (512k).

Signed-off-by: Vincent Veron <vincent.veron@st.com>
 2019-10-16 11:53:52 +01:00
jeromecoutant b3a14b5ead STM32WB : LSI clock selection when LSE is not available 2019-10-16 11:53:52 +01:00
jeromecoutant 7272fe0613 STM32H7: LSI clock selection when LSE is not available 2019-10-16 11:53:52 +01:00
int_szyk 7411db1deb Change the LSI_VALUE according to documentation 2019-10-16 11:53:52 +01:00
jeromecoutant c9f7798df5 STM32WB ADC : Consecutive VBAT values reading was not possible 
Add Stop after read
 2019-10-16 11:53:52 +01:00
jeromecoutant 74a24ea88d STM32H747 license update 2019-10-16 11:53:52 +01:00
jeromecoutant 2008be1c0d DISCO_H747I single core M7 introduction 2019-10-16 11:53:52 +01:00
jeromecoutant 46b310304a STM32H747xI introduction 2019-10-16 11:53:52 +01:00
jeromecoutant 08fe757f14 STM32H743 files move 2019-10-16 11:53:52 +01:00
jeromecoutant 0f12e65b9c STM license file update 
Some code have been copied from ST Cube deliveries.
ST copyright is then needed.
 2019-10-16 11:53:52 +01:00
dolphin\\gena 6176f066f4 formatting 2019-10-16 11:53:52 +01:00
dolphin\\gena 8d734ee055 bad formatting correction 2019-10-16 11:53:52 +01:00
dolphin\\gena 495ba7b92c indents correction 2019-10-16 11:53:52 +01:00
dolphin\\gena 13c202b828 rename macro 2019-10-16 11:53:52 +01:00
Martin Kojtal a35663b171 ST pinmap: remove endif mistype 2019-10-16 11:53:52 +01:00
Martin Kojtal 908e7a3e9f ST pinmap: Fix the style 2019-10-16 11:53:52 +01:00
dolphin\\gena 8e9511e435 formatting 2019-10-16 11:53:52 +01:00
dolphin\\gena 954552a7d1 fix mistypes 2019-10-16 11:53:52 +01:00
dolphin\\gena 7bc2aae435 formatting issue 2019-10-16 11:53:52 +01:00
dolphin\\gena e8be6505c4 mistype fix 2019-10-16 11:53:52 +01:00
dolphin\\gena f84a2df116 Add pin speed controlling interface 2019-10-16 11:53:52 +01:00
int_szyk c138ef8baa Change LSI_VALUE in STM implementation. 
Wrong LSI value might be causing problems witch watchdogs.
 2019-10-16 11:53:52 +01:00
int_szyk c423602161 AStyle 2019-09-12 17:18:37 +01:00
int_szyk aeb15e9cce Fix problem with low level lp_ticker STM wrapper 2019-09-12 17:18:37 +01:00
jeromecoutant 55d60f3c25 Add USB support for DISCO_L4R9I 2019-09-03 16:43:05 +02:00
jeromecoutant 425d63856c STM32L4 USB: remove EndpointAbort support 2019-09-03 14:23:05 +02:00
Martin Kojtal 940d3fdf60
Merge pull request #11291 from LMESTM/STM32_OSPI_QSPI_fallback_support 
Stm32 ospi qspi fallback support
 2019-09-02 12:26:55 +02:00
Martin Kojtal a65ed8c3d8
Merge pull request #11303 from jeromecoutant/PR_H743ZI2_480 
NUCLEO_H743ZI2 : increase system clock from 400 MHz to 480 MHz
 2019-08-29 17:10:06 +02:00
jeromecoutant bb1388be8e NUCLEO_L4R5ZI: add QSPI_x definition 2019-08-29 14:17:33 +02:00
Martin Kojtal 8ef742a49c
Merge pull request #11370 from u-blox/ublox_odin_driver_os_5_v3.7.1_rc1 
Driver Updates + ARMC6 driver support + WIFI fixes
 2019-08-29 13:35:06 +02:00
jeromecoutant f13072490c NUCLEO_L4R5ZI : add OSPI pins for QSPI 2019-08-29 12:11:28 +02:00
Laurent Meunier 8401c2ea31 STM32: Few fixes and tidy-up in qspi_api 2019-08-29 11:17:46 +02:00
jeromecoutant be78084a8b NUCLEO_H743ZI and NUCLEO_H743ZI2: clock configuration cleanup 2019-08-29 10:52:24 +02:00