8 Commits (b69dc2bdae61bb0401ea98d7d565640c7ca33be0)

Author	SHA1	Message	Date
Jonatan Antoni	14150bb7c6	Core(A): Fixed __FPU_Enable function not to mess registers. (#589) ... - Enhanced function to use only two temporary registers. - Added used registers to clobber list. Change-Id: If7c9462ed4424781e40379fbe12a5e4e3257920f	2019-05-21 19:25:58 +09:00
Kevin Bracey	00c9005b4e	[CMSIS_5]: Updated to ca812421	2019-04-10 14:41:35 +03:00
Russ Butler	342841aa0f	[CMSIS_5]: Updated to 0b521765	2018-08-25 20:41:00 -05:00
Bartek Szatkowski	8afbd66763	[CMSIS_5]: Updated to 49ac527a	2018-05-14 12:18:20 +01:00
Jonatan Antoni	063717d90d	Core(A): Changed macro __DEPRECATED to CMSIS_DEPRECATED. (Issue #287) ... __DEPRECATED conflicts with a predefined macro in GCC C++ mode.	2017-12-21 14:09:25 +09:00
Jonatan Antoni	2f06202a9b	Core(A): Refactored L1 Cache maintenance to be compiler agnostic. ... - Added L1 Cache test cases to CoreValidation. - Adopted FVP Cortex-A configs to simulate cache states.	2017-12-21 14:09:25 +09:00
Robert Rostohar	56602562ad	Core(A): Updated __FPU_Enable function (VFP register count detection)	2017-12-21 14:09:25 +09:00
Bartek Szatkowski	a03591d6e3	CMSIS/RTX: Update CMSIS and RTX to 22b68c ... This includes Cortex A support and directory reshuffle.	2017-11-01 09:25:42 +00:00