CMSIS repo does not support pre-processor defines, hence multiple assembly
files are added for secure/non-secure and floating point tools.
Mbed OS tools support assembly file pre-processing, but the build system
does not support multiple assembly files for each target, hence updating
the assembly files.
1. Patch RTX so irq_cm4f.S files work with no FPU targets
2. Patch RTX so irq_armv8mml.S files to work with and without FPU
2. Patch RTX so irq_armv8mml.S and irq_armv8mbl.S files to work with secure and
non-secure builds
(cherry picked from commit 094662790a)
In case of ARM compiler, idle and timer thread stack though assigned
to `.bss.os` section since not zero initialized are part of `data` section.
In this commit, we are moving stacks of idle and timer thread to bss
section and thereby saving ROM space.
(cherry picked from commit ba92372b8d)
mbed OS used older RTX4 version and with osThreadDef accepting only 3
parameters, to preserve compatibility we hardcode the 'instances'
parameter to 1.
(cherry picked from commit 428acae1b2ac15c3ad523e8d40755a9301220822)
(cherry picked from commit 4360b7bbf8)
For single-threaded apps __iar_Initlocks() is not required and must
not be called because the proper IAR library is brought in only if
"--threaded_lib" is defined in the linker command.
Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts
Assembler in rtx_core_ca.h is on the whole unified syntax such that it
should work fine if assembled as either ARM or Thumb-2.
The exception was __get_PSP, which uses STM^, which is only available
in ARM state.
Flagging for this function was incorrect, except for IAR - it switched
assembler state without telling the compiler, meaning that the resulting
assembler output could be incorrect, and that the function itself would
not be correctly marked as an ARM function - the CPU would enter in
Thumb state.
Alternative fix would be to switch to System mode, which would work
as either ARM or Thumb-2 assembler, like the rest of the file, but
this is the minimal change.
Fixes#526.
Optimize the tick computation in the following ways:
1. Use relative time rather than absolute time
2. Replace multiplication/division pair with just multiplication
or division:
"* 1000000ULL / OS_TICK_FREQ" -> "* US_IN_TICK"
"* OS_TICK_FREQ / 1000000" -> "/ US_IN_TICK"
The low power ticker wrapper layer adds a large amount of interrupt
latency. This can cause dropped bytes at a baud of 115200 on some
devices. To prevent this by default use the microsecond ticker for
tickless on devices which make use of the low power ticker wrapper.
Matches rest of RTOS class timeout parameters by using the unit name. Remove ambigious statement in reference to 0 ms being no-timeout as a timeout of 0 causes the function to not block and return immediately (osWaitForever is used as no timeout as it will wait forever)
Memory model for RTOS and No RTOS was initially single stack and heap,
only few targets implemented 2-region RAM model.
2-region RAM model is applied for all toolchains and targets.
GCC: __wrap__sbrk was implemented for 2-region ram model, with switch to 2-region
for all targets, we do not need target specific implementation of this API
Also _sbrk is WEAK function, hence can be over written in target folder for
special cases
Earlier if interrupt stack is specified it was used and remaining section of
IRAM was used to allocate heap, if stack is not specified heap section was
reduced by isr stack size and it was added at the end of RAM
With 2-region RAM support interrupt stack will always be specified.
CMSIS repo does not support pre-processor defines, hence multiple assembly
files are added for secure/non-secure and floating point tools.
Mbed OS tools support assembly file pre-processing, but the build system
does not support multiple assembly files for each target, hence updating
the assembly files.
1. Patch RTX so irq_cm4f.S files work with no FPU targets
2. Patch RTX so irq_armv8mml.S files to work with and without FPU
2. Patch RTX so irq_armv8mml.S and irq_armv8mbl.S files to work with secure and
non-secure builds
1. Revert "CMSIS/RTX: __FPU_USED to be set based on HW FPU support"
This reverts commit b4f5bed7e75c21927c954a50d40422b81a1de5a0.
2. Revert "CMSIS/RTX: Update Armv8M IAR 8.x assembly files - add END"
This reverts commit b228cd9db0.
3. Revert "CMSIS/RTX: Pre-processor defines used for assembly"
This reverts commit 287121ffdc.
4. Revert "CMSIS/RTX: Patch RTX so irq_cm4f.s files work with no FPU targets"
This reverts commit cc2e0517e1.
In case of ARM compiler, idle and timer thread stack though assigned
to `.bss.os` section since not zero initialized are part of `data` section.
In this commit, we are moving stacks of idle and timer thread to bss
section and thereby saving ROM space.
Main thread in Mbed OS is statically allocated and was not available in call
stack of Keil MDK. The RTX5 kernel requires statically allocated thread
information objects that are placed into a specific section to enable RTOS
thread awareness in Keil MDK. This fix is to keep main thread in specific
section of memory.
Add missing END to the IAR assembly files. In future this commit should be
merged to other assembly file commit, when performing CMSIS update.
287121ffdc
The DEVICE_FOO macros are always defined (either 0 or 1).
This patch replaces any instances of a define check on a DEVICE_FOO
macro with value test instead.
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
Make the option positively named, and as it is a platform config
option make sure it only affects platform code.
HAL functions still remain available even if platform is told not
to use them.
Make the following changes:
-Allow a vector specific ARM MPU driver by defining MBED_MPU_CUSTOM
-Allow ROM address to be configured for ARMv7-M devices by
setting the define MBED_MPU_ROM_END
-Add ROM write protection
-Add new functions and lock
-enable at boot
-disable during flash programming
Enable the MPU as part of the boot sequence and disable it before
starting a new application. Also add reference counted MPU lock and
unlock functions to allow code to execute from ram when necessary.
On platforms using both tickless and the low power ticker wrapper
so much of the background stack is used that it overflows. To
ensure the background thread's stack doesn't overflow increase this
size by 256 bytes when tickless is enabled. Worst case usage
on the NUCLEO_F476RG was recorded at 656 when tickless is
turned on so this increased size should safely prevent overflows.
Only deep sleep when the wakeup time is more than
MBED_CONF_TARGET_DEEP_SLEEP_LATENCY ms in the future.
This ensures that RTOS events are handled at the correct time. Note -
when deep sleep is allow interrupt latency may still be as high as
10ms.
Cruz Monrreal
jeromecoutant
Kevin Bracey
Bartek Szatkowski
deepikabhavnani
Martin Kojtal
RFulchiero
d-kato
Russ Butler
kegilbert
Oren Cohen
Oren Cohen
Przemyslaw Stekiel
Antti Kauppila
Alastair D'Silva
Marc Emmers
Senthil Ramakrishnan
Jeroen de Bruijn
Amanda Butler
Mel W
paul-szczepanek-arm
Steve Cartmell