b3583f04cf
Merge pull request #12464 from jeromecoutant/PR_ETHERNET
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STM32 EMAC : add configuration choice and connection check
2020-03-03 16:04:18 +00:00
3e30033822
DISCO_L4R9I correct LED pins
2020-03-03 13:36:57 +01:00
bad9c57085
Merge pull request #12460 from mprse/spi_init_nc_fix
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Allow MISO/MOSI set to NC during SPI initialisation (fix for issue #12435 )
2020-03-03 09:56:47 +00:00
1b40076376
STM32 EMAC : more configurable
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- PHY default configuration can be changed
- AutoNegotiation
- Speed
- DuplexMode
- PHY register offset can be updated depending on chosen PHY
All unused parameters are cleaned.
2020-03-02 16:19:26 +01:00
2d93a4578d
Merge pull request #12451 from jeromecoutant/PR_QSPI_TRACE
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STM32 : enable MBED trace for QSPI
2020-02-27 10:02:46 +00:00
9977ace2c9
STM32 : enable MBED trace for QSPI
2020-02-20 12:20:24 +01:00
a1570f936f
STM32WB : Add ReadMe file
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Help on FW update procedure
2020-02-20 09:20:44 +01:00
9d016022b6
STM32WB clean SetSysClock
2020-02-20 09:20:44 +01:00
ebae0e56d4
STM32WB align deepsleep functions with CubeFW
2020-02-20 09:20:43 +01:00
9f5ced30dc
Merge pull request #12415 from jeromecoutant/PR_H7README
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STM32H7 : add readme file for dual core use
2020-02-19 12:52:10 +00:00
713be4fd77
STM pin_function(), pin_mode(): return immediately when given pin is NC
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Additionally, remove redundant pin checks against NC when above functions are used.
2020-02-19 11:46:59 +01:00
c6a6984ab8
Allow NC for MISO or MOSI while initializing SPI
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Static pinmap extension required to use pin_function() and pin_mode() functions instead of pinmap_pinout(). Unfortunatelly pin_function() does not allow passing NC pin.
Call pin_function() and pin_mode() only if MISO/MOSI pin is not NC.
2020-02-18 13:38:43 +01:00
065a79e48a
STM32H7: add README file for dual core use
2020-02-17 16:21:20 +01:00
d66b39de18
STM32L5 : Add DISCO-L562E support
2020-02-14 17:49:40 +01:00
f0969022b8
STM32L5 : add QSPI support
2020-02-14 17:49:33 +01:00
7658681a9e
Merge pull request #12409 from LMESTM/Fix_lpuart_deep_sleep
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FIX: LPUART clock source selection should be left to serial driver
2020-02-13 09:45:41 +00:00
3fd071404e
FIX: LPUART clock source selection should be left to serial driver
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The clock source selection of LPUART depends on System clocks but also on
the serial baudrate. There is a specific computation done in serial driver
targets/target_STM/serial_api.c
At first start-up the LPUART1 clock selected in SetSysClock was anyway
overridden by the serial driver, so this was of no effect. But in case
of deep sleep SetSysClock is called again, while the driver isn't, so
SetSyClock was corrupting the serial clock configuration.
So let's remove these few lines of code which are causing trouble.
2020-02-11 17:14:45 +01:00
c1eaf2c358
Merge pull request #12380 from mprse/DISCO_L475VG_IOT01A_add_gpio_pinmap
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DISCO_L475VG_IOT01A: Add a list of restricted GPIO pins for testing
2020-02-11 11:58:53 +00:00
7fd5119b89
Merge pull request #12341 from fkjagodzinski/fix-stm-hal_fpga
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STM32L4: Fix the UART RX & TX data reg bitmasks
2020-02-10 13:21:31 +00:00
2368a07244
STM32: Fix the UART RX & TX data reg bitmasks
2020-02-07 16:23:50 +00:00
3a71f86235
DISCO_L475VG_IOT01A: Add a list of restricted GPIO pins for testing
2020-02-07 11:41:32 +01:00
ae635d5cd4
STM32L4: Fix the UART RX & TX data reg bitmasks
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The existing logic was insufficient to properly handle odd and even
parity setting, e.g. serial_getc() returned 9-bit data for 8O1
transmission format.
2020-02-06 14:07:51 +01:00
32675cc6ac
Merge pull request #11874 from fkjagodzinski/armc6_build-enable_lto_for_release
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ARMC6: Add a build profile extension with the link-time optimizer enabled
2020-02-05 14:42:16 +00:00
e3ad1cae55
Merge pull request #12334 from AriParkkila/cell-c030-r412m
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Update cellular drivers/tests for UBLOX_C030_R412M
2020-02-05 12:50:11 +00:00
841b846b46
Merge pull request #12362 from ABOSTM/L0_CUBE_HAL_REWORK_NO_MORE_OVERRUN
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TARGET_STM: L0 CUBE SPI async mode send next byte after previous one is read
2020-02-05 10:17:13 +00:00
cee2a352a7
Merge pull request #12357 from ABOSTM/F103_ADC3_NOT_SUPPORTING_COMMON_SETTINGS
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TARGET_STM32F1: don't set ADC common register when ADC doesn't support it
2020-02-04 15:24:51 +00:00
315220832f
TARGET_STM: L0 CUBE SPI async mode send next byte after previous one read
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In STM32 Cube HAL, in interrupt mode (async),
2 bytes can be prepared in hardware registers without any read
(1 in regular register, the other in shift register),
but Only 1 RX byte can stored in hardware register, specially when there is no hardware FIFO.
If interrupt handling is fast enough, each read is made in parralele of the write.
But if interrupt handling is too long or is interrupted for too long,
it can happen that one read byte is lost (overrun).
For STM32F4, Tickless has been deactivated to avoid such issue.
For STM32L0, we don't want to deactivate tickless,
because those chips are specially design for lowpower.
So instead of removing SPI async mode,
we propose to change the HAL behavior specially for L0:
each byte is send only when previous read is performed.
Thus only 1 RX byte at a time which is saved in hardware register.
This prevent overrun, but it introduceS some latency between each byte send,
this is why it is not applied to all STM32 families.
2020-02-04 13:26:49 +01:00
8db3b40a7b
STM: change rtc irq handler name
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Fix for the error caused by lto on armc6 compiler:
L6137E: Symbol RTC_IRQHandler was not preserved by the LTO codegen but is needed by the image.
lto optimization cause that local symbol RTC_IRQHandler(from rtc_api.c)
somehow interferes with global symbol RTC_IRQHandler (from startup_stm32f070xb.S)
Changing local RTC_IRQHandler to _RTC_IRQHandler fixes problem
2020-02-04 12:29:52 +01:00
250e58134f
Merge pull request #12286 from pea-pod/target-nucleo_l452re-p
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Add new target: NUCLEO_L452RE-P
2020-02-03 16:34:36 +00:00
03b03feb8d
TARGET_STM32F1: don't set ADC common register when ADC doesn't support it
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STM32F103ZE: ADC3 doesn't support common settings.
__LL_ADC_COMMON_INSTANCE(ADC3) returns 0
2020-02-03 15:56:49 +01:00
0f4a9867be
Merge pull request #12332 from jamesbeyond/analogIn_fix
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FIX: Disable Analogin D13(PA_5) on some NUCLEO targets
2020-02-03 12:44:07 +00:00
f7d9850fe7
Disable Analogin D13(PA_5) on some NUCLEO targets
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- pins are connected to the LED, can't be used as analogin
2020-02-03 11:39:31 +00:00
02c5e0806f
Merge pull request #12350 from maciejbocianski/fix_fpga_i2c_test
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implements i2c_free for STM
2020-02-03 09:56:59 +00:00
0b634e54b4
implement i2c_free for STM family
2020-01-31 14:51:54 +01:00
95996fb924
disable PA_8 i2c pin on NUCLEO_F411RE
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pin PA_8 by default is connected to MCO
2020-01-31 14:48:00 +01:00
ba5dd4d8c1
Merge pull request #12153 from mprse/spi_fpga_test_extend
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Hackathon: Increase coverage of the SPI master FPGA test
2020-01-31 15:00:02 +02:00
91464b2729
Merge pull request #12306 from jeromecoutant/PR_STM32L5_NUCLEO
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STM32L5: NUCLEO-L552ZE-Q new target
2020-01-29 16:07:44 +02:00
d6f8fece69
Cellular: Enable IP over PPP on UBLOX_C030_R41XM
2020-01-29 03:03:35 -08:00
f7c4693747
Add new target: NUCLEO_L452RE-P
2020-01-27 18:41:18 -06:00
ceaf562a11
Merge pull request #12283 from jeromecoutant/PR_STM32WB
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STM32WB - Update CubeDriver from v1.0.0 to v1.4.0
2020-01-25 11:54:29 +00:00
e4d0629d18
STM32L5 : Introduce NUCLEO_L552ZE_Q board
2020-01-23 17:55:07 +01:00
c1386cf52d
STM32L5 : update generic STM files for L5
2020-01-23 17:54:55 +01:00
bee5d44a1f
STM32L5: add API L5 family files
2020-01-23 17:54:52 +01:00
5d59c99b99
STM32L5: TOOLCHAIN automatic updates
2020-01-23 17:54:41 +01:00
77e5bb45b9
STM32L5: STM32Cube_FW_L5_V1.0.0 files
2020-01-23 13:30:31 +01:00
25da13bc18
STM32WB remove extra file
2020-01-23 10:53:09 +01:00
9f42a58d5a
STM32H7 correct PWMOUT
2020-01-21 16:03:17 +01:00
3657f902d3
STM32Cube_FW_WB_V1.4.0 - STM32WB55xx part
2020-01-20 17:24:46 +01:00
7a5da6109f
STM32Cube_FW_WB_V1.4.0 - STM32WB50xx part
2020-01-20 17:24:46 +01:00
c39a13d10c
STM32Cube_FW_WB_V1.4.0 - template part
2020-01-20 17:24:45 +01:00
b4f3b0799d
STM32Cube_FW_WB_V1.4.0 - STM32_WPAN part
2020-01-20 17:24:45 +01:00
08184d7ac9
STM32Cube_FW_WB_V1.4.0 - HAL_DRIVER part
2020-01-20 17:24:44 +01:00
d6e4b15c1a
STM32Cube_FW_WB_V1.4.0 - CMSIS part
2020-01-20 17:24:43 +01:00
339846a1bb
STM32WB cleanup
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- BLE feature is mandatory
- remove clock source selection
- license alignment
- startup file from Cube delivery
- linker script alignement
2020-01-20 17:24:28 +01:00
8f6171f8b0
STM32WB - BLE restructure
2020-01-20 16:10:55 +01:00
8c76a43d3c
STM32WB - New directory structure
2020-01-20 16:10:55 +01:00
d6e69ef57b
Merge pull request #12208 from hugueskamba/hk-replace-uartserial-st
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ST targets: Replace UARTSerial references with BufferedSerial
2020-01-17 08:19:09 +00:00
88f48d240e
Merge pull request #12237 from mprse/stm_serial_free_fix
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STM serial free: Set pin function only if pin is defined (not NC)
2020-01-15 13:02:20 +01:00
978a9665f0
Merge pull request #12201 from jeromecoutant/PR_G0REFACTOR
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TARGET_STM: FW driver files refactor proposition
2020-01-15 12:59:49 +01:00
8a938ea777
STM serial free: Set pin function only if pin is defined (not NC)
2020-01-10 14:59:28 +01:00
759ce271c2
Merge pull request #12200 from MultiTechSystems/fix_PeripheralPins
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Minor fixes for peripheral pins on Dragonfly Nano
2020-01-09 13:17:01 +01:00
dbb0695311
Merge pull request #12202 from LMESTM/Increase_MSI_Freq_out_of_deep_sleep
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Increase MSI clock frequency when exiting deep sleep
2020-01-09 10:49:20 +01:00
03cff0a02c
ST targets: Replace UARTSerial references with BufferedSerial
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BufferedSerial is UARTSerial renamed to convey the original purpose of
the class. It is the recommended buffered I/O serial class.
2020-01-08 08:34:20 +00:00
022c0eb7dc
Increase MSI clock frequency when exiting deep sleep
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This will optimize down the time it takes to restore the clock
settings when getting out of deep sleep.
If 48MHz is available let's use it, otherwise at least 4MHz should be
available for any MCU with MSI.
2020-01-07 17:59:33 +01:00
9448ded044
STM32G0: Update G071xx toolchain files with default files
2020-01-07 17:00:30 +01:00
cf2dfcbc60
STM32G0: introduction of G030/G031/G041/G070/G081 sub-families
2020-01-07 16:07:18 +01:00
57f144ec66
STM32G0: remove MBED patch
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Goal is to remove all mis-aligment with official ST CUBE delivery
2020-01-07 16:05:34 +01:00
631ed0c0b3
STM32G0: move us_ticker_data.h file to family level
2020-01-07 16:02:08 +01:00
6d780d8773
STM32G0: move cmsis_nvic.h file to Sub-family level
2020-01-07 16:01:45 +01:00
7dd31d0319
STM32G0: move TOOLCHAIN files to Sub-family level
2020-01-07 16:00:40 +01:00
fd52eb46d1
STM32G0: move files to TARGET_STM32G0/STM32Cube_FW
2020-01-07 16:00:16 +01:00
6875d0318e
STM32G0: move files to TARGET_STM32G0/STM32Cube_FW/CMSIS
2020-01-07 15:57:04 +01:00
f322d87d43
STM32G0: move files to TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver
2020-01-07 15:56:19 +01:00
94ead7adb2
Minor fixes for peripheral pins on Dragonfly Nano
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1. PG8 should be labeled I2C3 not I2C1.
2. PC0 is dedicated to measuring system voltage.
2020-01-07 08:52:34 -06:00
5d71e69f6a
Merge pull request #12186 from mprse/fix_for_issue_12172_stm_serial
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STM serial init: Set pin function only if pin is defined (not NC)
2020-01-07 11:38:00 +01:00
79d16ae8f7
STM serial init: Set pin function only if pin is defined (not NC)
2020-01-03 14:14:26 +01:00
fc2a71064d
Merge pull request #12068 from rajkan01/feature_bare_metal
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Enabling small C library option and deprecating uARM toolchain
2020-01-03 11:35:48 +00:00
e29cb193ca
Added missing define for Quectel UG96
2019-12-27 16:04:10 +01:00
ca7848d854
Refactored away onboard_modem_api because it is not needed at all
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All targets must implement soft_- and hard_power_on/off() functions which are practically same what onboard_modem_api offered.
These were seen as a duplicate features and therefore we removed this.
All targets involved have been updated to reflect the changes
2019-12-27 16:04:10 +01:00
5cedd3320c
STM32F0: clean main-thread-stack-size setting
2019-12-23 12:29:40 +01:00
c27c03c784
STM32 remove unused INITIAL_SP macro
2019-12-23 12:29:40 +01:00
7202b77834
STM SPI capabilities: rx/tx buffers can have different sizes
2019-12-20 12:56:11 +01:00
7609eb4741
Merge pull request #12113 from mprse/can_init_fix
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Fix for issue #12104 (STM32 can_init_freq() ignores frequency)
2019-12-20 11:24:05 +01:00
957dca2082
Enabling small C library option and deprecating uARM toolchain
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- By default, Mbed OS build tools use standard C library for all supported toolchains.
It is possible to use smaller C libraries by overriding the "target.default_lib" option
with "small". This option is only currently supported for the GCC_ARM toolchain.
This override config option is now extended in the build tool for ARM toolchain.
- Add configuration option to specify libraries supported for each toolchain per targets.
- Move __aeabi_assert function from rtos to retarget code so it’s available for bare metal.
- Use 2 memory region model for ARM toolchain scatter file for the following targets:
NUCLEO_F207ZG, STM32F411xE, STM32F429xI, NUCLEO_L073RZ, STM32F303xE
- Add a warning message in the build tools to deprecate uARM toolchain.
- NewLib-Nano C library is not supporting floating-point and printf with %hhd,%hhu,%hhX,%lld,%llu,%llX
format specifier so skipping those green tea test cases.
2019-12-19 10:05:11 -08:00
bef36f5f3e
Merge pull request #12093 from ABOSTM/SUPPORT_NUCLEO_G071RB
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TARGET_STM: add support of board NUCLEO_G071RB
2019-12-19 15:26:08 +00:00
fffc30ffda
STM CAN: remove CAN_INIT_DIRECT macro
2019-12-18 10:43:55 +01:00
b1b0673622
Merge pull request #12086 from ABOSTM/FLASH_API_64B_ALIGNMENT
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TARGET_STM: fix flash api 64bit address alignment on L4 and WB
2019-12-17 16:46:21 +00:00
8b0a5c2e4b
Merge pull request #12099 from J91Olivier/stm32f4_baud_rate_calculation_fix
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Implemented recommended fix from https://github.com/STMicroelectronic …
2019-12-17 16:27:19 +00:00
378f8c2b26
Merge pull request #12067 from jeromecoutant/PR_IRQ_CRITICAL
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STM32 GPIO IRQ : add a critical section in gpio_irq_init
2019-12-17 16:23:44 +00:00
e0e280aeaf
optimize can_init(): call can_init_freq() with default freq
2019-12-16 14:09:54 +01:00
6a3e343ec6
Fix for issue #12104 (STM32 can_init_freq() ignores frequency)
2019-12-16 13:16:51 +01:00
ef5da02a68
Implemented recommended fix from https://github.com/STMicroelectronics/STM32CubeF4/issues/5
2019-12-13 10:48:38 +02:00
7c52aa59ec
TARGET_STM: add support of board NUCLEO_G071RB
2019-12-12 14:00:04 +01:00
9e3ad13d5e
TARGET_STM: fix flash api 64bit address alignment on L4 and WB
2019-12-11 18:32:42 +01:00
06da49984f
Merge pull request #12069 from jeromecoutant/PR_ASTYLE
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STM32: astyle update
2019-12-11 08:01:19 +01:00
9317bea756
STM32 GPIO INIT in critical section
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critical section added in gpio_irq init and free functions
to protect shared code structures
Note that other functions are protected in API level in InterruptIn
2019-12-10 15:59:56 +01:00
22ab94a1c9
TARGET_STM32F74: fix IAR SIZE check in linker scripts
2019-12-10 14:09:38 +00:00
e27f456a29
STM32F756xG: fix IAR RAM size check
2019-12-10 14:09:37 +00:00
bea83d02c2
STM32 TARGET_STM astyle corrections
2019-12-10 14:39:47 +01:00
e9cb9cb014
Merge pull request #12018 from jeromecoutant/PR_OLIMEX_EMAC
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STM32_EMAC cleanup
2019-12-05 14:03:46 +01:00
Martin Kojtal
jeromecoutant
Przemyslaw Stekiel
Laurent Meunier
Filip Jagodzinski
Alexandre Bourdiol
Maciej Bocianski
Qinghao Shi
Kevin Bracey
Ari Parkkila
pea-pod
Anna Bridge
Hugues Kamba
Leon Lindenfelser
Antti Kauppila
Rajkumar Kanagaraj
jaco.olivier