Fixed interrupt vector settings on M0 core. Wrong vector settings prevented
LP_TICKER from working, resulting in deep sleep tests failing on M0
or PSA variant.
Internal channels use is enabling ADC "internal path" which needs
to be disabled after measurement.
Same applied here for WB family as was done for others in #10143.
Typically the RTC clock is configured by RTC driver itself.
RNG on the other hand is shared with M0+ core and it is expected that
M4 turns it on at boot time.
When doing so, do not disbale GPIO clocks as they may be used by other
drivers !
As a result, debug will be disabled by default, but can be enabled by
either modifying code or selecting MBED debug profile.
Review HSE clock initialization to match with latest CUBE firmware.
Also there is no need to set the full clock tree again after deep sleep exit.
With this change we get a stable deep sleep mode (when allowed by CORDIO stack).
Until the CMSIS pack device name is officially deployed.
then we'll the name as can be found in Keil CMSIS pack
<!-- ************************* Device 'STM32WB55RG' ***************************** -->
<device Dname="STM32WB55RGVx">
<memory id="IROM1" start="0x08000000" size="0x001000000" startup="1" default="1" />
<memory id="IRAM1" start="0x20000000" size="0x000040000" init="0" default="1" />
<algorithm name="CMSIS/Flash/STM32WB_M4.FLM" start="0x08000000" size="0x001000000" default="1" />
<feature type="QFP" n="68"/>
</device>
There is no need to add FIRST attribute to MAPPING_TABLE as the default
ordering is alphabetical order.
With this change, we don't have any warning with MBED2 and the sections
are properly ordered anyway in BLE cases.
In case of mbed2, BLE feature is not built.
As there is a MAPPING_TABLE in BLE feature which is not compiled in case
of mbed2, the linker reported the below error
[ERROR] "C:/Data/Workspace/mbed/BUILD/test/NUCLEO_WB55RG/ARM/MBED_2/
.link_script.sct", line 65 (column 6): Error: L6236E:
No section matches selector - no section to be FIRST/LAST.
Solution is to check whether BLE is enabled.
These files are not BLE specific, but also needed for some clock setting
for instance.
In order to compile an MBED2 application, we need to move the files.
- move hw_conf.h file to targets/TARGET_STM/TARGET_STM32WB directory as
this is used also out of BLE feature.
- create a dedicated hal_deepsleep function as the behavior in WB is a lot
different from other existing STM32 targets
- update clock tree configuration to directly clock the entire tree @ 32MHz
out of HSE. This is needed as we want to let the M0 core running without
any change on M0-side of clocks when M4 enters /exits deep sleep.
Needed for PSoC to deep-sleep for more than 2 seconds
Max sleep with 16 bit lp_ticker (before this change) : 2sec
Max sleep with 32 bit lp_ticker (after this change) : 36hours
The cache must be refreshed when we erase or program flash memory.
It fix 2 issues :
Fix#9934Fix#6380
This solution was initially proposed in #6380.
Signed-off-by: Vincent Veron <vincent.veron@st.com>
The OS timer of RZ/A1 uses P0 clock, so until now it has been set the value of P0 clock in SystemCoreClock.
Changed the system clock value to set to SystemCoreClock.
Changed to refer to P0 clock macro instead of SystemCoreClock in OS timer processing.
Ashok Rao
Leszek Rusinowicz
Laurent Meunier
bcostm
jeromecoutant
Ganesh Ramachandran
junichi.katsu@uhuru.jp
Brian Daniels
Vivek Pallantla
Lei Zhang
Mahesh Mahadevan
Vincent Veron
ecoromka
d-kato
ccli8
Oren Cohen