mbed-os

Commit Graph

Author	SHA1	Message	Date
Przemyslaw Stekiel	87902a8e76	Add SCLK and SIN stats to SPIMasterTester. It has been found that there is a problem with the new K66F SPI driver when clock polarity is high. After setting clock polarity to high SCLK line is still low. When transmission starts and CS is asserted (in case of manual CS handling) SCLK signal is invalid (low). After first transfer SCLK idle state becomes high. SPI implementation on FPGA test shield is resistant on this bug and transmission is successful. The problem has been found on two boards communication test where transmission fails. The idea is to add support to the FPGA test shield to catch such errors and verify this in the test.	2019-05-27 09:48:33 +02:00
Russ Butler	b3332129b2	Check in files for the FPGA CI Test Shield Bring all the FPGA CI Test Shield C and C++ driver files into mbed-os as the component FPGA_CI_TEST_SHIELD. When this component is enabled all the files that are needed to communicate with, update firmware on and run testing with the FPGA are built.	2019-05-07 15:10:47 -05:00

Author

SHA1

Message

Date

Przemyslaw Stekiel

87902a8e76

Add SCLK and SIN stats to SPIMasterTester.

It has been found that there is a problem with the new K66F SPI driver when clock polarity is high.
After setting clock polarity to high SCLK line is still low. When transmission starts and CS is asserted (in case of manual CS handling) SCLK signal is invalid (low). After first transfer SCLK idle state becomes high.
SPI implementation on FPGA test shield is resistant on this bug and transmission is successful. The problem has been found on two boards communication test where transmission fails.

The idea is to add support to the FPGA test shield to catch such errors and verify this in the test.

2019-05-27 09:48:33 +02:00

Russ Butler

b3332129b2

Check in files for the FPGA CI Test Shield

Bring all the FPGA CI Test Shield C and C++ driver files into mbed-os
as the component FPGA_CI_TEST_SHIELD. When this component is enabled
all the files that are needed to communicate with, update firmware on
and run testing with the FPGA are built.

2019-05-07 15:10:47 -05:00

2 Commits (a03f5ff4e6f6f54904b18ebaa0119c714b041d89)