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4 Commits (97709f52ec368cf6baa4dfcd8df4c33a6087ca16)

Author SHA1 Message Date
Kevin Bracey 703e44031c Add atomic loads and stores and barriers 
Add atomic load and store functions, and add barriers to the existing atomic
functions.

File currently has no explicit barriers - we don't support SMP, so don't
need CPU barriers.

But we do need to worry about compiler barriers - particularly if link time
optimisation is activated so that the compiler can see inside these
functions. The assembler or intrinsics that access PRIMASK for
enter/exit critical act as barriers, but LDREX, STREX and simple
volatile pointer loads and stores do not.
 2019-01-18 09:32:04 +02:00
Kevin Bracey 6f757a5824 LoRAWAN: volatile bool -> atomic_flag 
Now we have a proper atomic flag API, use it rather than a volatile
cheat.
 2019-01-14 11:59:25 +02:00
Antti Kauppila 0f8cfd8631 LoRa regions unittested, stubs licences revisited 2018-09-27 10:49:07 +03:00
Antti Kauppila 9f9aa4a210 cellular unittests ported to googletest framework 2018-09-17 12:07:43 +03:00