As part of work to improve the debugging of exceptions, have
Mbed OS make an effort to make exceptions more precise in debug builds
at the cost of performance.
Related pyOCD work:
https://github.com/mbedmicro/pyOCD/pull/430
The ACTLR register itself is conditional on chip revision, but its
bit definitions were always defined.
Make the the bit definitions also conditional, so it is possible to
produce portable code that sets DISDEFWBUF if available:
#ifdef SCnSCB_ACTLR_DISDEFWBUF_Msk
SCnSCB->ACTLR |= SCnSCB_ACTLR_DISDEFWBUF_Msk;
#endif
(cherry-picked from CMSIS b2b04dbeece0a046556bfc320bef6b20bef3f16f)
This is achieved by checking whether the board can allocate a certain memory
chunk (threshold) and skipping the test if it can't.
This should prevent these boards from failing in CI.
targets.json was not specifying the same macro name as the code was
checking for, so setting was ineffective.
Making this work tripped up not-supported checks in ARMv8-M - rather than deal
with making this work, support it instead.
Both ARMv7-M and ARMv8-M slightly reduce code size and runtime impact if
mpu-rom-end is 0x1fffffff, using one fewer region.
This means default setup for ARMv8-M now requires 5 regions, with
mpu-rom-end set to default 0x0fffffff, but this can be put back to 4 by
changing the setting.
As we build for a specific CPU, a runtime check for number of MPU
regions in release builds is not worthwhile. Make it an assert only.
Saves a little space in develop images, a lot in release.
Switch to higher-level calls and macros, and fix an error in the ARMv8-M
version - "inner" attributes were not being set correctly due to a
copy/paste error - "outer" was being set twice.
This means RAM would have been marked WTRA rather than WBWA for the
inner cache.
Slightly reduces ARMv7-M init code size by feeding region number
into RBAR instead of using RNR.
QPI may have slightly better performance, but it is not supported by all targets.
It requires register setup between each Read and Program/Erase commands,
which might damage the overall performance eventually.
Issue was seen with below example
EventQueue q1;
EventQueue q2;
void main() {
while( true ) {
q1.chain( &q2 ); // Chain q2 to q1
q1.chain( NULL ); // Remove chain from q1
//This second step should free the memory from the chained q2 event.
}
}
Memory allocated from q1 slab was freed for q2, which will result in
memory leak.
### Description
PR #8607 will cause problems for the NRF52832 and the NRF52840
in the online compiler starting with 5.10.2. This PR prevents this problem
by using a toggle in `targets.json` to enable these new defines for every
target except for the NRF52832 and NRF52840.
### Pull request type
[x] Fix
[ ] Refactor
[ ] Target update
[ ] Functionality change
[ ] Docs update
[ ] Test update
[ ] Breaking change
Anna Bridge
Kevin Bracey
David Saada
Amir Cohen
jeromecoutant
Mel W
Cruz Monrreal
test user
vervaekejonathan
Martin Kojtal
offirko
deepikabhavnani
Jimmy Brisson
Naveen Kaje