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11 Commits (96a1c1ae8fc7589554658e80fb098f0af5055367)

Author SHA1 Message Date
Chun-Chieh Li f45ca72f11 [M252KG] Remove TRNG support 
Reasons to remove TRNG support:
1.  M252 just has 32KiB SRAM and cannot afford mbedtls application.
2.  Implementing TRNG HAL with PRNG H/W has security concern.
 2019-09-27 17:50:48 +08:00
Chun-Chieh Li 0168304e5b [M252KG] Add BSD-3-Clause license for BSP files 2019-09-27 17:45:57 +08:00
Chun-Chieh Li 967effe59f [M252KG] Free up peripheral pins in peripheral free-up HAL API 
Without free-up of peripheral pins, peripheral pins of the same peripheral may
share by multiple ports after port iteration, and this peripheral may fail with
pin interference.
 2019-09-27 17:45:56 +08:00
Chun-Chieh Li 38aaee0c1a [M252KG] Support GPIO input pull-high/pull-low 
In Nuvoton, only new-design chips support GPIO input pull-high/pull-low modes.
Targets not supporting this feature are listed below:

- NUMAKER_PFM_NANO130
- NUMAKER_PFM_NUC472
- NUMAKER_PFM_M453
 2019-09-27 17:45:56 +08:00
Chun-Chieh Li 1447d9049f [M252KG] Fix redundant call to UART IRQ handler 
Honor RxIrq/TxIrq to avoid redundant call to UART IRQ handler.

This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-uart.
 2019-09-27 17:45:55 +08:00
Chun-Chieh Li d9217ed77a [M252KG] Fix redundant SPI clock generation 
Fix SPI clocks are generated redundantly at the end of transfer.

This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-spi/
SPI - async mode.
 2019-09-27 17:45:55 +08:00
Chun-Chieh Li c68af32a4c [M252KG] Fix I2C NACK error 
Fix logic error on replying NACK at the end of transfer.

This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-i2c/
i2c - test single byte read i2c API.
 2019-09-27 17:45:55 +08:00
Chun-Chieh Li 0917a0d5a6 [M252KG] Fix IP initialization sequence 
Better IP initialization sequence:
1. Configure IP pins
2. Select IP clock source and then enable it
3. Reset the IP (SYS_ResetModule)

NOTE1: IP reset takes effect regardless of IP clock. So it doesn't matter if
       IP clock enable is before IP reset.
NOTE2: Non-configured pins may disturb IP's state, so IP pinout first and then
       IP reset.
NOTE3: IP reset at the end of IP initialization sequence can cover unexpected
       situation.
 2019-09-27 17:45:54 +08:00
Chun-Chieh Li 4bb7fde6b5 [M252KG] Exclude USB UART from testing 
USB UART is dedicated to USB COM and so must exclude from FPGA CI testing.
 2019-09-27 17:45:54 +08:00
Chun-Chieh Li cd73422345 [M252KG] Force enum PinName to 32-bit 
NU_PINNAME_BIND(...) requires enum PinName to be 32-bit to encode module
binding information in it.
 2019-09-27 17:45:54 +08:00
Chun-Chieh Li 36278618ad Support Nuvoton's NUMAKER_M252KG target 2019-09-27 17:45:52 +08:00