It has been found that there is a problem with the new K66F SPI driver when clock polarity is high.
After setting clock polarity to high SCLK line is still low. When transmission starts and CS is asserted (in case of manual CS handling) SCLK signal is invalid (low). After first transfer SCLK idle state becomes high.
SPI implementation on FPGA test shield is resistant on this bug and transmission is successful. The problem has been found on two boards communication test where transmission fails.
The idea is to add support to the FPGA test shield to catch such errors and verify this in the test.
Bring all the FPGA CI Test Shield C and C++ driver files into mbed-os
as the component FPGA_CI_TEST_SHIELD. When this component is enabled
all the files that are needed to communicate with, update firmware on
and run testing with the FPGA are built.
Maciej Bocianski
Przemyslaw Stekiel
Russ Butler