I modified the lack of copyright in the below header files that I added for commonizing the RZ_A1 related files.
- targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/mbed_drv_cfg.h
- targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/mbed_drv_cfg.h
Read By group type response can return 4 descriptor discovered when the remote server have 4 descriptors with a 16 bit UUID. The handle, UUID pair get stored in a ble_gattc_desc_t that is 20 bytes long.
This PR increase buffer size to handle this use case.
hal_critical_section_enter() is safe to call multiple times, however
hal_critical_section_exit() is only called on the last exit from a
critical section. This will cause a mismatch in the counter and the
interrupt state will never be restored if the critical section is
nested. Change this to a bool so that the interrupt save state is
tracked for hal_in_critical_section() to work correctly.
STM32L0, L4, F7 and few F4 chip are supporting LPTIM feature.
We propose to allow user to use LPTIM for MBED LowPowerTimer API instead of using RTC wakeup timers.
By default, all targets that are supporting this feature have been configured.
I made be available in common whatever the board related to RZ_A1 in the below files.
- Since there are the table code of Pinmap differs for each board, I moved the code to "PeripheralPins" file for each board, and changed to include PeripheralPins.h.
analogin_api.c, can_api.c, gpio_irq_api.c, i2c_api.c, pinmap.c, port_api.c, pwmout_api.c, serial_api.c, spi_api.c and us_ticker.c
- Since there are some board-specific processes, I enclosed the processes with "#ifdef" and rearranged the functions to make be easier to enclose.
can_api.c, ethernet_api.c and serial_api.c
- Since there are the driver configuration values differs for each board, I added "mbed_drv_cfg.h" file for each board and defined macros for the values, and changed to refer to the macros.
can_api.c, gpio_api.c, pwmout_api.c and rtc_api.c
In "targets/TARGET_RENESAS" folders, same as Cortex-M targets, I changed the folder structure to combine files that can be shared as RZ/A1 related.
And I renamed the folder name to "TARGET_RZ_A1XX" in order to make commonality explicit.
- "targets/TARGET_RENESAS" folder
<before>
\targets\TARGET_RENESAS\TARGET_RZ_A1H
\targets\TARGET_RENESAS\TARGET_VK_RZ_A1H
<after>
\targets\TARGET_RENESAS\TARGET_RZ_A1XX
Call underlying HAL implementation to enter critical section/disable interrupts
before incrementing the global critical section counter.
Modify HAL implementations to track first entrances to the critical section and
only update the saved state on first enter.
Currently, trng_api.c is located in targets/ and AES/DES/SHA alter. are located in mbedtls/.
They have shared crypto code.
If they could locate at same location e.g. mbedtls/, the shared crypto code placement would be more reasonable.
Add counter to track crypto init among crypto sub-modules. It includes:
1. Enable crypto clock
2. Enable crypto interrupt
As counter gets zero, crypto clock is disabled to save power.
which can be called from diferent contexts.
Orginal nordic critical primitives must been called in pairs
from exacly the same function. As mbed hal call it in separate
methods, so they are not suitable here.
As it does not share the codebase with RZ A1H, it needs to be disabled until
bring it up to date with the latest changes to cmsis. There are changes
regarding caches, mmu and others
Merged from the existing TARGET_DISCO_F413ZH code (which has the same MCU)
and TARGET_NUCLEO_F412ZG code (which has the same Nucleo-144 board and
pinout).
Although the extened RTC is supported by #5363 commit ("Add support and tests for extended RTC"), it seems that the changes was overlooked in RZ_A1H_api.c.
So I added the changes with reference to other rtc_api.c.
I changed disable_irq() / enable_irq() to core_util_critical_section_enter() / core_util_critical_section_exit() by utilizing "mbed_critical" function in the below drivers.
- serial_api.c
- us_ticker.c
I added the below definitions for working "Dynamic Stack" and "Dynamic heap" on Mbed OS by referencing with the codes of Cortex-M target board.
"ISR_STACK_START", "ISR_STACK_SIZE", "INITIAL_SP", "HEAP_START" and "HEAP_SIZE"
By updating to the codes of CMSIS5/RTX5, GIC_SetConfigration() function was added for Cortex-A, this function is set the interrupt configuration using GIC's ICFGR register. Therefore, I added this function to satisfy Cortex-A interrupt spec in the below files.
"can_api.c", "ethernet_api.c", "gpio_irq_api.c", "i2c_api.c", "spi_api.c" and "us_ticker.c"
For supporting tp CMSIS5/RTX5, I changed the start-up processing of 3 toolchains(ARMCC, GCC_ARM, IAR) and updated the register definition of PEACH specific.
In addition,
I changed the linker script files to implement the dynamic HEAP the same as Cortex-M targets.Since GR-PEACH's HEAP was a fixed area, I changed the label name(ZI_DATA to RW_IRAM1) and replaced the allocation of STACK/HEAP.
Set buffer for 1 sample in analogin_read_u16. Before it assumes the
buffer is set outside by the higher layer. Now it's temporarily
located on the stack since only the ADC value is returned.
Pending official update from STM, add memory barriers to the Ethernet
HAL code for the STM32F7xx family.
Cortex-M7 has a merging write buffer that is not automatically flushed
by accesses to devices, so without these DMBs, we sometimes lose synch
with the transmitter.
The DMBs are architecturally needed in every version of this HAL, but
adding just to the STM32F7 version for now to clear test, as the
problem has only been observed on Cortex-M7-based devices.
Fixes#5622.
Filter numbers 14 to 27 are reserved for dual CAN configuration.
However, CAN3 operates in single CAN configuration according to the
reference manual).
CAN_2 and CAN_3 are enum and not #define and this causes compilation error with GCC_ARM
Instead put back the test of CAN_NUM (which are defined in can_device.h).
Ensure all instance memory blocks meet 4 byte alignment requirement
without relying on compiler's or liker's optional settings:
- gpioMemory[] for adi_gpio_Init()
- aRtcDevMem0[] for adi_rtc_Open()
- i2c_Mem[] or I2C_Mem[] for adi_i2c_Open()
- spi_Mem0[], spi_Mem1[], spi_Mem2[] or SPI_Mem[] for adi_spi_Open()
Add RSF synchro during init
Set a better WakeUp clock for long wake up period in order to stay in sleep mode
Use rtc_isenabled function before init as rtc_init is called at each set_time call
- Maintain compatible code for ARM 5 and ARM 6 while default alignment
settings differ.
- Instance memory containing memory pointers must be 4 byte aligned for
all compilers regardless compilers' settings.
- uint32_t is recommended to replace uint8_t for instance memory
declaration because uint32_t guarantee 4 byte alignment.
Based on the Mbed OS website the A3 is connected to "DAC", however there
is no define for DAC. In order to get the Realtek RTL8195AM to even compile
with mbed-os-example-client now, we must have the A3 defined - it is one of
the standard Arduine header pins. Therefore, setting it as NC.
A4-A5 are not connected either, so adding them as "NC" as well.
Realtek will hopefully push a proper fix sooner or later, if there is a
more meaningful define for the A3 pin. They do state however that the
A0-A3 pins are not GPIO capable anyway.
Ref: https://os.mbed.com/platforms/Realtek-RTL8195AM/
1. move ota region 1 from 0x00b000 to 0x040000
2. move ota region 2 from 0x0c0000 to 0x120000
3. refactor bootloader header as follows:
uint32_t tag;
uint32_t ver;
uint64_t timestamp;
uint32_t size;
uint8_t hash[32];
uint8_t campaign[16];
uint32_t crc32;
where,
a. hash is the sha256 checksum of the payload.
b. crc32 is the crc32 checksum of headers from tag to campaign.
4. Call NVIC_SystemReset for soft reset.
Signed-off-by: Tony Wu <tung7970@gmail.com>
signals are lost. It was observed at last for tests-api-spi ci-test-shield's
test.
This patch introduce usage of sdk5 origin implementation in which
sd_nvic_critical_region_enter/exit is calling each time critical region
is enter/exit. This fixes the issue.
Timer code was written based on integer multiple HF clock frequencies. EFR32 doesn't conform to that (38.4), and so the timestamp ticks were off by 1%. Enough to trip up some CI tests on TB_SENSE_12 (#5496)
- serial_init, serial_free and serial_baud function moved from serial_device.c (specific to each STM32 family) to serial_api.c (common STM32 file)
- default baudrate value was hardcoded to 9600
- Value is set now to MBED_CONF_PLATFORM_STDIO_BAUD_RATE for STDIO
- Value is set now to MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE for other use
- UART init will not be stopped before calling serial_baud function
This patch handles the case of SPI slave mode without MISO (NC).
In case MISO is not connected, we consider that SPI will be configured in
3 wires mode (CLK / MOSI / CS, but no MISO). In this case, the MOSI line
is bi-directional : SPI_DIRECTION_1LINE.
But as this is not supported yet in slave mode, we force it to
SPI_DIRECTION_2LINES. In this case slave SPI will receive data on MOSI
but nothing will be sent back to master as MISO is not connected.
Old lp_ticker handles past event, but it has a bug with premature go-off.
The bug can re-produce on mbed-os-tests-mbed_drivers-lp_timeout/mbed-os-tests-mbed_hal-lp_us_tickers (mbed-os commit: 9c1fd48529).
Because upper layer (mbed-os/hal/mbed_ticker_api.c) has handled past event, this code can be removed from lp_ticker.
The similar fix also applies to us_ticker.
Re-casting with tmp the uint8_t* pData pointer to uint16_t* brings a
memory corruption and typically can corrupt the size parameter. This
is fixed with this commit.
STM32 Internal ticket reference : 39116
Fixed issues raised from ARM PR review and removed the unsupported platform.
- Fixed an issue where the TRNG is read even though it may not be ready;
- Added configuration to ensure the buffering mode is disabled so only 8-bit bytes are generated;
- Moved the TRNG device handle into the trng_t structure.
Removed undefined spi slave related functions.
- Added error checking for trng_get_bytes function;
- Added curly brackets to single line conditions for some files;
- Changed rx and tx buffers in serial module as local variables;
- Removed some unused code and some minor formatting corrections;
- Minor i2c & spi updates for github pull request;
- Added function definition for spi_master_block_write.
Added default delay and sample times for the ADC during initialization.
- Added code to clear stack variable in trng_get_bytes upon exiting the
function;
- Remove lp ticker functionality as the timer hardware does not satisfy
lp timer requirements.
Added a check for the STUCK bit before reading the RNG data register to ensure there are no hardware faults.
- Removed .mbedignore to work around some exporter issues;
- Added #includes to some of the driver data C files for them to build on their own.
For api usage like DigitalOut led(LED1, 1) the hal function gpio_write()
sets the output before f. gpio_mode() is called. gpio_mode() clears the
output as it take never writen parameters (gpio_cfg_t.init_hight).
This patch use internal hardware register of GPIO output instedad of above paramiter latch
for retaining proper writen state.
The Page size has been set to 1 byte instead of the previous 256.
Although 256 is the physical page size, the driver supports
writing 1 byte at a time.
The computation of the sector number in GetSector for 2MB flash sizes
consists in adding an extra constant for 2MB dual bank (12 as in
ADDR_FLASH_SECTOR_12), then going through the same address check as if it
was an address of the first sector.
That means that we need to modify tmp and address as if it was a first bank
address, which we're doing here by sub_stracting 0x100000 delta.
Three main issues:
1) The 0x13 special case section in write data in ncs36510_i2c.c didn't have a write++ command.
2) In the same write function, the WDAT8 command was put before the 0x13 section and this is not correct
3) Needed to add wait_us(0) before and after the register writes for apparent clock domain crossing delay times until registers are stable in HW
There were also a handful of other tweaks related to general code maintenance and moving some status register checks to the proper locations.
TIMER2_7_IRQ is shared among several timer sources, including
us_ticker. Raising TIMER2_7_IRQ pending bit will trigger the timer
interrupt, but the timer interrupt handler will not know which timer
source this interrupt is for. This patch sets timer load value to one
tick and force us_ticker to fire almost "immediately".
TIMER2_7_IRQ is handled through a common interrupt handler, and
is automatically cleared. Therefore, there is no need to clear IRQ.
The underlying timer HAL treats load value as micro-seconds and does
conversion internally. Therefore, simply pass micro-seconds to timer
HAL without converting to tick first.
Signed-off-by: Tony Wu <tung7970@gmail.com>
Cribbed from 4bf42f2e20
I'm not sure if if there are any copyright issues here with what is
effectively a set of config files. A few folks have been bugging me (and
the redbear folks) for these changes, so I wanted them somewhere
centralized.
The generic Flash support for L4 and L0 families is already there,
but was not activated by default on 2 recentely added boards:
DISCO_L475VG_IOT01A and DISCO_L072CZ_LRWAN1
This is done now.
HAL_RNG_GetRandomNumber is a deprecated API and replaced here with
a call to HAL_RNG_GenerateRandomNumber.
Doing so, we also rework the driver to use the 4 bytes returned by a call
to HAL_RNG_GenerateRandomNumber instead of 1 byte out of 4.
HAL_RNG_GenerateRandomNumber was not returning any error code, so now
we can also check the return code.
Remove redundant memory regions, and merge multiple RAM regions into one
to solve ielftool zero padding issue.
The side effect is less control over object files placement. It's all up
to linker's best effort.
Signed-off-by: Tony Wu <tonywu@realtek.com>
lp_ticker driver is the known registered user of RTC handler API.
In case, a lp_ticker is set in the past, the lp_ticker_fire_interrupt
will be called which itself sets the RTC interrupt as pending by calling
NVIC_SetPendingIRQ(RTC_WKUP_IRQn). This all happens without actual
programing of the RTC wake-up.
As a result the RTC HW and corresponding HAL layer doesn't expect an
interrupt to happen and will not call HAL_RTCEx_WakeUpTimerEventCallback.
To sove this situation, we will not use HAL_RTCEx_WakeUpTimerEventCallback
weak definition but rather call handler whenever an RTC interrupt fires.
Change implementation of timeout to one that is using us_ticker hal.
Timeout is now configurable by I2C_TIMEOUT_VALUE_US macro and this
value will be imported if will be defined externaly.
- Added curly brackets to single line conditions in gpio_qpi.c and gpio_irq_api.c;
- Changed rx and tx buffers in serial module as local variables;
- Minor i2c & spi updates for github pull request;
- Added function definition for spi_master_block_write.
- Added a configuration call in trng_init to make sure the TRNG buffering mode is disabled, so only 8-bit bytes are returned;
- Moved the TRNG device handle into the trng_t structure;
- Fixed some formatting errors in the adc driver.
Fix ARMC6 guard typo introduced in commit 4f3f0cc9cc (Make Realtek link)
While at it, remove redundant ISR_STACK_SIZE assignment for ARMCC.
Signed-off-by: Tony Wu <tonywu@realtek.com>
Target of LPC1769 links to mbed LPC1768.
The PinNames.h has conditional compile for the pin names.
LWIP lpc17xx emac driver modified to allow LPC1769 target
Fixes#5115.
`analogin_read_u16` returns a value in the range `0x0000 - 0xFFF0`
since the resolution of the ADC is 12 bits. However, in
`analogin_read` this value gets divided by `0xFFFF` assuming the range
is `0x0000-0xFFFF`. This causes a small error in the value returned by
`AnalogIn::read` for the EFM32 target.
The allocation of GPIOTE channels for DigitalIn is unwanted behavior.
This caused early run-out of channels for InterruptPin.
This patch replacing input configuration that is using gpiote driver by configuration that is
using gpio hal.
Previous the voltage range was set to 1.2 from SoC internal reference source.
This caused problem with testing. It is unexpected that range is much
shorter than vdd as well.
The voltage range was extended using SoC build in analog prescaler (set to 1/3).
From RM:
32.3.2.6 Interrupts during IAP
The on-chip flash memory is not accessible during erase/write operations. When the user
application code starts executing the interrupt vectors from the user flash area are active.
The user should either disable interrupts, or ensure that user interrupt vectors are active in
RAM and that the interrupt handlers reside in RAM, before making a flash erase/write IAP
call. The IAP code does not use or disable interrupts.
The use of mktime was causing a fault when called in interrupt handler because on GCC it lock the mutex protecting the environment, To overcome this issue, this patch add dedicated routine to convert a time_t into a tm and vice versa.
In the process mktime has been optimized and is now an order of magnitude faster than the routines present in the C library.
commit f7bc126 (Re-work Rtl8195AM ticker) tried to address ticker drifting
issue, but in fact broke ticker functionality. This patch adjusts us_ticker
porting to unbreak it, and to fix the following tests:
mbed-os-tests-mbed_drivers-ticker
mbed-os-tests-mbed_drivers-timeout
mbed-os-tests-mbedmicro-rtos-mbed-isr
mbed-os-features-frameworks-utest-tests-unit_tests-minimal_async_scheduler
mbed-os-features-frameworks-utest-tests-unit_tests-case_control_async
mbed-os-features-frameworks-utest-tests-unit_tests-case_async_validate
Changes are:
1. Dont disable timer after every us_ticker interrupt. That basically
breaks ticker functionality.
2. Fine-tune us to tick conversion macro. Previous conversion method
yields 1 tick drift every 2 ms.
3. Remove special placement of ticker objects. No longer necessary.
Signed-off-by: Tony Wu <tonywu@realtek.com>
As reported by MBED user Fran6Jack:
I2C bus are usually 5V tolerant on all STM32 processor.
If an external device on the I2C bus requires 5V operation,
we usually acheive it by using 5V external pull-ups on the bus.
Since signaling uses open-drain output on I2C for both signal SCL and SDA
any 5V tolerant MCU will work on a 5V I2C bus. Having pull-up activated on a 5V externally pull bus, cause the pin to clamp on the STM32 die diode and could damage the IC (There is a note in STM32 datasheet specifying this issue).
It is understood by all the community that I2C bus should always be
externally pulled by physical resistor. I2C initialization should then
be ALWAYS OpenDrainNoPull by default.
Up to now, this I2C driver was setting pull up by default as it helps
basic testing, like 1 master and 1 slave, conencted with 2 wires without
any external pull ups. This will not work anymore after this commit and
applications tests or examples needs to be modified to explicitely
configure pull ups ... But it is safer to follow reference manual
guidelines.
When the RTOS is present and the tickless mode is not implemented, it is
expected that the next tick issued by the Systick timer will wake up the MCU.
However nothing prevents an implementation of the ARM architecture to gate the
systick clock signal upon sleep entry.
Therefore on those targets sleep shall be prohibited if the RTOS is present and the
tickless mode is not implemented.
To ease life of porters , a new option has been added in the device add list:
STCLK_OF_DURING_SLEEP. This option expose that the target turn of the systick
clock during sleep.
Targets which exhibit such behavior shall add this define in their device_has list.
There was some interesting stuff here.
* ARMC6 treats assembly the same as GNU, but has a different startup
function, so we branch the asm there
* Incorrect discriminant, probably copied from other ports
Add NOPs after deep sleep to prevent unexpected behavior. It appears
that the first one or two instructions after deep sleep do not get
executed properly.
Note - This is a temporary workaround. For a more robust solution
the NCS36510 needs to investigate the root cause of this issue.
The NCS36510 is not suitable for tickless, since its LP ticker cannot
be scheduled fast enough. This is because it takes four 32KHz clock
cycles before these writes take effect - ~120us.
Decrease the interrupt stack from 2k down to 1k so there is enough
ram to build all the tests with tickless enabled. In general, targets
should not need an interrupt stack greater than 1k with mbed-os.
Some Cortex-M0 devices, such as the nrf51, don't have the SysTick.
Instead, these targets use a software interrupt to simulate SysTick.
Add the hooks in the tickless code to support these devices. Targets
which do not have SysTick should now define NO_SYSTICK in targets.json
and implement mbed_get_m0_tick_irqn to add os suport.
This patch also removes os tick handling from the existing devices
(nrf51) since this is now handled in common code.
IAR 8.x compiler throws error for emac_interface_t constructor
rtw_emac.cpp@220,0: [Pe1790]: the default constructor of "emac_interface"
cannot be referenced -- it is a deleted function
Error is because new object is created of structure with constant member.
Resolved it by using malloc instead new.
Rather than Unlocking flash during flash object creation, and leaving
the flash possibly continuously unlocked a(s object might bever be freed),
we decide to Unlock then Lock again at each erase or program call.
Fixing regression introduced in commit
"Ticker: add fire interrupt now function".
In above mentioned commit, the management of timestamp being in the past
has been moved to higher layer (hal/mbed_ticker_api.c), but the reset of
oc_int was missing when implementing the new us_ticker_fire_interrupt
function - which is fixed now.
After reset the MCR register content needs to be restored so we're
introducing the can_registers_init function to be called at the first
init stage, but also after reset. We also store the can frequency to
go through the initialisation phase again.
In order to apply the same mode in case of reset, we store the current
requested mode in the HAL structure.
To make storage in a single place, we also change can_monitor to call
can_mode function as they actually acting on same registers.
Instead of a static object, this will make driver
instantiation more robust and allow to re-use init
configuration on a need basis.
The CANName struct member is actually the CAN registers base address,
which is now available in the CanHandle.Instance field, so we don't need
CANName anymore.
Since mbed-os 5.4.3, something increased foot print of mbed-os and the applications that were barely fitting in started to spill.
IAR toolchain for LPC176x target family is set to use 2 RAM regions (32K each). RAM region
2 is being used for ETH/USB and 1 is being used for vector table, stack/heap/static data.
In this commit we have decreased heap size allocation from 8K to 7K so that the is more room for stack and static data.
If NVIC_NUM_VECTORS is larger than the space allocated by the vector
table in ram (__ram_vector_table_size__) then the call to mbed_cpy_nvic
during boot will corrupt valid data, which can lead to a crash. This
patch fixes the declared number of vectors on the KL27Z, KL43Z and
KL82Z to fix this crash.
Adding flash API support to STM32F7 family. The code is derived from
F4 family one. The memory topology is described in flash_data.h files
and the flash_api.c implementation manages the 2 possible memory types (1
or 2 banks).
Users of FlashIAP usually get the minimum programable size
by calling flash.get_page_size(), so let's return the minimum
to allows a most efficient usage of flash.
For F4 devices, this is 1 byte.
For L0 and L1 devices, this is a word (4 bytes).
For L4 devices, this is a double word (8 bytes).
First add the flash_data.h that describe the flash memory topology,
and also activate FLASH support for the corresponding targets.
This is a 1,5MB flash memory device which contains 15 sectors, where
sectors 12 to 15 are 128KB sectors. So flash_api.c needed has been
updated to differentiate between this flash memory and the 2MB ones
by checking existence of sector 16 instead of sector 12.
UBLOX_ODIN_EVK_W2 is missing the abstract button definitions originally
introduced with PR https://github.com/ARMmbed/mbed-os/pull/4249.
Fix two tab to spaces issues on the go as well.
It is required to enable AFIO clock before using __HAL_AFIO_REMAP_xy
macros, which was missing here. Without clocks enable, the remap
actually doesn't occur. This would possibly cause some PIOs (part of
PB_3, PB_4, PA_13, PA_14, PA_15) to not behave as expected.
In most cases AFIO clock was enabled in stm_pin_SetAFPin function, so
that this bug was not visible. But there were few cases left were
stm_pin_DisconnectDebug would be called first. A typical case was
with GCC_ARM in case a DigitalInOut variable is declared as global.
On F410RB, the size reserved to vectors with ARM toolchains was not properly
defined,which was not the case for other toolchains.
This would cause few tests to fail like EXAMPLE_1 with below error:
HOST: Unknown property: mbed assertation failed: _ptr == (T *)&_data, file: C:/github/mbed/BUILD/mbed/platform/SingletonPtr.h, line 91
Enabling SPI causes the clock to be output by default.
Most devices will not care about extra clock cycles, especially as long
as chip select is not active, nevertheless this may cause side issues
with other devices especially during init phase.
This was actually the case with a 3 wire device (LPS22HB sensor).
In case MISO is not passed at SPI init, then we consider a 3 wires SPI
configuration is requested, which corresponds to SPI_DIRECTION_1LINE
configuration parameter in STM32 HAL layer.
We're then handling this specific case of SPI_DIRECTION_1LINE,
in spi_master_write or spi_master_block_write, we call to HAL API
Functions 'serial_break_set' & 'serial_break_clear' wrongly removed during 'SERIAL_FC disabled, critical section API Updation' commit.
Due to this 'mbed compile' command for GCC_ARM tool fails to compile.
- Removed the patterned LED sequence, all boards now use the 4 fast pulse, 4 slow pulses LED sequence.
- Changed the LED used from LED_RED to LED1. Only 58/174 targets seem to define LED_RED but they all define LED1.
- Removed all ERROR_RED and ERROR_PATTERN definitions from targets/targets.json
Use ADDR_FLASH_SECTOR_12 as this is defined by target (the flash size varies, for
instance for some F437xx is up to 2MB (2nd bank might not be there)).
1. With mbed OS 5, mbed_sdk_init() is ensured to call before C++ global object constructor.
2. Refine startup file with GCC_ARM toolchain related to this modification.
1. With mbed OS 5, mbed_sdk_init() is ensured to call before C++ global object constructor.
2. Refine startup file with GCC_ARM toolchain related to this modification.
1. Rearrange SDRAM and SRAM layout. Move timing critical code to SRAM,
and the rest to SDRAM.
2. Add bootloader that's capable of FOTA over mbed cloud.
Signed-off-by: Tony Wu <tonywu@realtek.com>
- default value is the same as before patch
- system_stm32l4xx.c file is copied to family level with all other ST cube files
- specific clock configuration is now in a new file: system_clock.c (target level)
- nvic_addr.h file is now in TARGET_STM level
- default value is the same as before patch
- system_stm32l1xx.c file is copied to family level with all other ST cube files
- specific clock configuration is now in a new file: system_clock.c (target level)
- default value is the same as before patch
- system_stm32l0xx.c file is copied to family level with all other ST cube files
- specific clock configuration is now in a new file: system_clock.c (target level)
- default value is the same as before patch
- system_stm32f7xx.c file is copied to family level with all other ST cube files
- specific clock configuration is now in a new file: system_clock.c (target level)
- default value is the same as before patch
- system_stm32f3xx.c file is copied to family level with all other ST cube files
- specific clock configuration is now in a new file: system_clock.c (target level)
- default value is the same as before patch
- system_stm32f2xx.c file is copied to family level with all other ST cube files
- specific clock configuration is now in a new file: system_clock.c (target level)
- default value is the same as before patch
- system_stm32f1xx.c file is copied to family level with all other ST cube files
- specific clock configuration is now in a new file: system_clock.c (target level)
- default value is the same as before patch
- system_stm32f0xx.c file is copied to family level with all other ST cube files
- specific clock configuration is now in a new file: system_clock.c (target level)
The FlashIAP is supposed to have access to the full application
memory, so the address scope has been changed to encompass
the entire external flash.
The address translation has also been changed to reflect the memory
layout in the documentation:
Realtek Ameba1 Memory Layout: 5.1 Flash Memory
In this commit, the analogin_s structure is moved to commonn_objects.h file
to limit the duplicaion.
The ADC handle is moved from a global variable to a struct member of the
analogin object. This allows multiple ADC instances to work correctly.
Note that State needs to be explicitely set to HAL_ADC_STATE_RESET
because the object is not zero initialized.
TXE indicates that a byte can be written to UART register for sending,
while TC indicates that last byte was completely sent. So the TXE flag
can be used in case of interrupt based Serial communication, to allow
faster and efficient application buffer emptying.
Also TXE flag will be erased from the interrupt when writing to register.
In case there is nothing to write in the register, the application is
expected to disable the interrupt.
The RXNE flag is getting cleared when reading Data Register so it should
not be cleared here. Especially in case of high data rate, another byte of
data could have received during irq_handler call and clearing the flag
would read and discard this data which would be lost for application.
MAX32630FTHR gets BLE, uses timer peripheral 5 for HCI timing
libexactLE update for 610,620
Fixup hal_sleep and hal_deepsleep for 620
LEDn outputs now forced to open-drain
fire_interrupt function should be used for events in the past. As we have now
64bit timestamp, we can figure out what is in the past, and ask a target to invoke
an interrupt immediately. The previous attemps in the target HAL tickers were not ideal, as it can wrap around easily (16 or 32 bit counters). This new
functionality should solve this problem.
set_interrupt for tickers in HAL code should not handle anything but the next match interrupt. If it was in the past is handled by the upper layer.
It is possible that we are setting next event to the close future, so once it is set it is already in the past. Therefore we add a check after set interrupt to verify it is in future.
If it is not, we fire interrupt immediately. This results in
two events - first one immediate, correct one. The second one might be scheduled in far future (almost entire ticker range),
that should be discarded.
The specification for the fire_interrupts are:
- should set pending bit for the ticker interrupt (as soon as possible),
the event we are scheduling is already in the past, and we do not want to skip
any events
- no arguments are provided, neither return value, not needed
- ticker should be initialized prior calling this function (no need to check if it is already initialized)
All our targets provide this new functionality, removing old misleading if (timestamp is in the past) checks.
Depending on families, different HAL macros are defined to check the
state of serial interrupts. In several cases, we can find only 1 macro:
__HAL_UART_GET_IT_SOURCE
Checks whether the specified UART interrupt has occurred or not
But in F0, F3, F7, L0, L4 there are 2 different macros
__HAL_UART_GET_IT
Checks whether the specified UART interrupt has occurred or not
__HAL_UART_GET_IT_SOURCE
Checks whether the specified UART interrupt source is enabled.
In the later case, __HAL_UART_GET_IT_SOURCE was being used so far,
but actually needs to be replaced by __HAL_UART_GET_IT. Using the right
macro, we also check the proper flags accordingly.
1. With mbed OS 5, mbed_sdk_init() is ensured to call before C++ global object constructor.
2. Refine startup file with GCC_ARM toolchain related to this modification.
Some I2C devices require specific zero length read/write sequences which
the HAL_I2C_IsDeviceReady() redirect interferes with. After Removing
these redirects, it was confirmed that zero length reads and writes
would both still work correctly for detecting presence/absence of an
I2C device on a bus.
The symbol Systick_Handler was defined as a weak symbol in us_ticker.c and
startup_nRF51822.s. While it work as expected when an application is compiled
from mbed OS source code it creates a duplicate symbol issue when mbed OS is
bundled as a library.
Do not ticker read in ISR, use reminder to schedule the next interrupt, this should make ticker much faster.
read - disable Timer0 while reading it, if ISR is pending just reread the time again via read() function
These 2 improvements should decrease time spent when reading/scheduling ticker
events.
In case we've run through the entire GPIOs loop, withouth finding a
matching interrupt, we're in the case of a spurious interrupt, let's
raise an error to track it down.
When disabling GPIO irq, also the falling / rising edge settings need
to be reset (EXTI_RTSR and EXTI_FTSR registers).
If not reset, the same EXTI line can be later enabled again with a wrong
Rising / Falling configuration. This was especially seen and reported in
ci-test tests-api-interruptin on NUCLEO_F446RE target where DIO2=PA_10 and
DIO6=PB_10 were successively tested: as they are sharing the same EXTI_LINE
(EXTI_10), this resulted in calling the irq_handler with wrong
IRQ_FALL/IRQ_RAISE parameter and donothing being called in loop.
This commit completely rewrote flash_api.c in a few places so kicked out changes from Master and accepted the branch changes.
F429 + F439 : changes after code review
GetSector has been rewritten
- default value is the same as before patch
- system_stm32f4xx.c file is copied to family level with all other ST cube files
- specific clock configuration is now in a new file: system_clock.c
- nvic_addr.h file is now in TARGET_STM level, and can be used everywhere
Use serial-box of Nordic nRF5 SDK to share resource between
SPI and I2C.
SPI is allocated from highest hw instance number resource in order
to allocate as many I2C instances as possible.
With default sampling time, the MBED2 and CI test shield tests would fail
because the stabilization slope of ADC is relatively slow.
ERROR (out:0.8000) - (in:0.7407) = (0.0593)
ERROR (out:0.9000) - (in:0.8354) = (0.0646)
ERROR (out:1.0000) - (in:0.9289) = (0.0711)
This is related to the 10kOhms resistors used to connect Ain to
Aout mounted on the CI shileds, and internal capacitance of L0 targets.
If connecting Ain and Aout with wires, bypassing the resistors, the test
is passed. So we're increasing the sampling time to let the automated
ci shiled tests PASS.
OK (out:0.8000) - (in:0.7863) = (0.0137)
OK (out:0.9000) - (in:0.8869) = (0.0131)
OK (out:1.0000) - (in:0.9844) = (0.0156)
Moving some code in common to be able to manage several ADC instances,
or several channels of an instance.
The change involves:
- moving dac_s structure definition to common_object.h
- create TARGET_STM/analogout_api.c and move fully common analog_out
functions in there
- rename analogout_api.c of each target family into analogout_device.c
to keep platform specific code
- update analogout_device.c to rely on obj->handle and obj->channel
- align analogout_init function as much as possible between families in
analogout_device.c files
ADC1 channel2 and ADC2 of few targets only have an output switch and no
buffer. This switch needs to be enabled, and also the buffer can be enabled
in order to reduce the output impedance on output, and to drive external
loads directly without having to add an external operational amplifier.
This allows a proper handling of multiple instances. Also this commit
stores the channel in the HAL format so that it can be re-used more easily
and call to HAL are straightforward.
"FAMILY_STM32" has been creeated with all common features.
All STM32 devices can now inherit from it.
This will simplify readability and maintainability.
+ VBLUno51 board:
Nordic nRF51822
Bluetooth Low Energy
DAPLink interface
Arduino UNO pinout compatible
4 Power
+ Wiki: https://vngiotlab.github.io/vbluno/
+ Pass all test case in mbed test suite
Signed-off-by: iotvietmember <robotden@gmail.com>
1. Support CMSIS_VECTAB_VIRTUAL feature
2. Reduce the register sync waiting time in LP ticker
3. Adjust the stack and heap size in GCC and IAR toolchains
This commit implements a SPI mode which will offer better performance
thanks to usage of Lower Layer API which use fewer registers access,
at the cost of lower robustness (no error management).
This patch updates CMSDK_CM3DS.h to remove the
DMA peripheral memory map and defines, as
that peripheral is not present in the system.
In addition, some define names where updated
concerning rtc. RTC_api was updated accordingly.
This patch also updates SMM_MPS2 to align defines and
comments.
Signed-off-by: Marc Moreno <marc.morenoberengue@arm.com>
This patch implements pin_function and gpio_set
with some fixes in the PinNames.
The patch also updates the serial and spi
drivers to use the pin_function.
Signed-off-by: Marc Moreno <marc.morenoberengue@arm.com>
Following
Merge pull request #4063 from LMESTM/17q2_L4_bootloader
the NUCLEO_L476RG binairies could not boot anymore.
The change done in #4063 was derived from work on NUCLEO_L429ZI target
which supports uvisor. The VECTORS defintiion is introduced as part of
uvisor support and requires further changes in ld file which were missing.
As uvisor is not considered yet, we remove VECTORS for now and will
introduce only when needed.
Remove HAL_Init and related code from SystemInit and move it to
mbed_sdk_init. The function SystemInit is called early in the boot
sequence before RAM is initialized or the VTOR is setup, so it should
not be used to perform the HAL initialization.
This fixes crashes due the vector table being used before it has been
relocated.
This reduces the number of loads inside of the .data copy loop by 3 by using one more register. It should work on any STM32 with at least 5 general-purpose registers. If only 4 are available, then 1 load could still be removed from the original implementation.
1. Add startup code and linker script for IAR and
GCC_ARM compilers.
2. Enable IAR and GCC_ARM compilers in targets.json.
Change-Id: I742a89ae73a4e5ede980a8af0821c3f0e5a461ef
Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>
Based on lwip_ethernetif.c skeleton file,
use init, receive and transfer
functionality of SMSC9220 Ethernet driver
for the lightweight IP stack.
Receive mechanism is interrupt driven.
HW buffer sizes:
Tx = 4608 bytes (MTU)
Rx = 10560 bytes
lwIP fine tuning:
mbed-os/features/FEATURE_LWIP/lwip-interface/lwip/src/include/lwip/opt.h
Change-Id: I0ea95650c65fb32cafb5c2d3dde11420c61dba66
Signed-off-by: Gabor Kertesz <gabor.kertesz@arm.com>
- Creates new target in targets.json
- Creates device specific files under ARM_SSG/CM3DS_MPS2 directory
- Driver layer files under CM3DS_MPS2 are based on Beid target
- Device specific files under CM3DS_MPS2/device are based on CMSIS_5 and Beetle
Change-Id: I29ea7a7f42b11cf25b516cce4b9255ab828ca019
Signed-off-by: Tamas Kaman <Tamas.Kaman@arm.com>
Signed-off-by: Marc Moreno <marc.morenoberengue@arm.com>
Define CMSIS_VECTAB_VIRTUAL for the M0 targets which have a
corresponding driver. The only M0 target missing this is the LPC4330_M0
which is not part of the 2 or 5 release.
Restore cmsis_nvic (cmsis_nvic.c and cmsis_nvic.h) files for the
implementations which use a mechanism other than the VTOR to set
interrupts. These are vendor specific and were done for M0 devices
which do not have a VTOR.
Note - There were two cmsis_nvic files which did not use the VTOR that
which not restored in this patch. This is because these targets were
not M0 devices and could use the new unified implementation instead.
These files are:
targets\TARGET_ARM_SSG\TARGET_MPS2\TARGET_MPS2_M0P\device\cmsis_nvic.c
targets\TARGET_ONSEMI\TARGET_NCS36510\device\cmsis_nvic.c
Note - cmsis_nvic.c and cmsis_nvic.h were initial removed in
(and restored from) the commit:
b97ffe8fdc -
"CMSIS5: Replace target defined NVIC_Set/GetVector with CMSIS implementation"
Note that this could have side effects on the application as it would
not be aware that data has been missed. This may be later solved by
adding an error management parameter to the Serial API in mbed.
The advantage is that the serial link can work again.
The use of mktime was causing a fault when called in interrupt handler because on GCC it lock the mutex protecting the environment, To overcome this issue, this patch add dedicated routine to convert a time_t into a tm and vice versa.
In the process mktime has been optimized and is now an order of magnitude faster than the routines present in the C library.
The Ameba RTC driver converts time_t to
second/minute/hour/day/month/year in rtc_write and back to time_t in
rtc_read. Replace this with an implementation which uses time_t
directly.
* Make memory sections configurable in linker files
* Dynamically determine vector location in flash for NVIC relocation
* Advertise bootloader support in targets.json
When using ARM Compiler 5, the RTX config hard-coded the heap and stack
sizes to specific values. This prevented the RTX HAL from dynamically
allocating unused memory as heap space.
Specifically, the HEAP_START define prevents this logic in RTX_CM_lib.h
from activating. The rest of the defines are also set in that header,
and should be removed from here.
* Using PinName as bitfield doesn't work without warnings, since NC
needs all 32 bits to be represented.
* lp_ticker should not be freed when interrupt is disabled, since this
will kill the timebase.
Add MBED_APP_START and MBED_APP_SIZE to the linker scripts
so the start and size of an image can be specified. This allows the
ROM to be split into a bootloader region and an application region.
Fix vector table
The address of the vector table is hardcoded to the start of flash.
This patch updates make it properly handle updating the VTOR with
a bootloader.
When initializing the RTC on Kinetis devices, handle the case where
the time overflow interrupt is pending and the case where the time
alarm flag is pending. These flags persist across reset and if not
handled will cause a crash when powering up the low power ticker.
This problem manifested as a lp_ticker test failure on the K22F and
K64F on CI only when running a nightly. This problem has been present
but was made obvious by PR #4094 which configures all tickers to
interrupt at least every MBED_TICKER_INTERRUPT_TIMESTAMP_MAX_DELTA
(~31 minutes). This caused the RTC alarm to fire 31 minutes after the lp_ticker
or lp_timeout test and caused the next run of the lp_ticker test to
crash on boot.
TimMasterHandle.Instance initialization can be removed from here,
because it will either have been already done previously,
or it will be done in the us_ticker_init() call immediately below.
Following previous fixes on 16 tickers handling, the overflow flag
condition will not happen anymore, so the work-around in place is
not needed anymore
This commit simplifies ticker interrupt set function and handler.
There were issues around the 16 bits timer wrap-around timing as we were
aligning interrupts with wrap-around limits (0xFFFF) and then reading
TIM_MST->CNT again in timer_update_irq_handler which could lead
to crossing case with the wrap-around (TIM_FLAG_UPDATE) case.
Now we're using the 16 lower bits of the timestamp as the reference from
using in set_compare and never changing it. There is also no need to set
comparator again in timer_update_irq_handler. This is more robust and
also more efficient.
Move to a single more reliable implementation of us_ticker_read()
There were historically 2 versions of us_ticker_read() implementation.
The one removed here was not reliable because us_ticker_read() can be
called in interrupt context which means that TIM_MST->CNT would have
wrapped around while SlaveCounter is not yet updated. So there is a need
to check the TIM_FLAG_UPDATE inside this function, which was not done in
the implementation that is removed here.
There is an easy default implementation of spi_master_block_write that
just calls spi_master_write in a loop, so the default implementation
of spi_master_block_write has been added to all targets.
As reported in issue #4214, there are seen issues seen first on
NUCLEO_F103RB in case of successive Reads of 1 byte at a time.
This issue is due to a wrong state management in the end of read sequence.
Also F1 i2c driver was not fully aligned to others, which is updated here.
There were still side effects, in particular on I2C master slave test,
when setting by default the Pin Speed for F1 family. So for F1 family,
let's do it only in case of Output which is the only case where this
actually applies on this family.
For STM32 targets using a 32-bit timer for the microsecond ticker, the
driver did not properly handle timestamps that are in the past. It
would just blindly set the compare register to the requested timestamp,
resulting in the interrupt being serviced up to 4295 seconds late
(i.e. after the 32-bit timer counts all the way around to hit the
timestamp again).
This problem can easily be reproduced by creating a Timeout object
then calling the timeout's attach_us() member function to attach a
callback with a timeout of 0 us. The callback will not get called for
over 2147 seconds, and possibly up to 4295 seconds late if no other
microsecond ticker events are getting scheduled in the meantime.
Now, after the compare register has been set, the timestamp is checked
against the current time to see if the timestamp is in the past, and
if so, the compare event is manually set.
NOTE: By checking if the timestamp is in the past after configuring the
capture register, we ensure proper handling in the case where the timer
updates past the timestamp while setting the capture register.
* Initialization clear interrupt status
* Remove state in management of interrupt
* Handle timestamp in the past
* Handle current seconds, even if out of the relative timestamp.
* Simplify interrupt handling logic.
For keep supporting external APIs with the same name (supposedly there are a larger
number of users of those APIs), BufferedSerial and ATParser are being renamed.
BufferedSerial becomes UARTSerial, will complement a future USBSerial etc.
ATParser becomes ATCmdParser.
* UARTSerial moves to /drivers
* APN_db.h is moved from platform to cellular/util/.
* Original CellularInterface is restored for backward compatability (again, supposedly there
are users of that).
* A new file, CellularBase is added which will now servce as the base class for all
upcoming drivers.
* Special restructuring for the driver has been undertaken. This makes a clear cut distinction
between an on-board or an off-board implementation.
- PPPCellularInterface is a generic network interface that works with a generic FileHandle
and PPP. A derived class is needed to pass that FileHandle.
- PPPCellularInterface provides some base functionality like network registration, AT setup,
PPP connection etc. Lower level job is delegated to the derived classes and various modem
specific APIs are provided which are supposed to be overridden.
- UARTCellularInterface is derived from PPPCellularInterface. It constructs a FileHandle and
passes it back to PPPCellularInterface as well as provides modem hangupf functionality.
In future we could proive a USBInterface that would derive from PPPCellularInterface and could
pass the FileHandle back.
- OnboardCellularInterface is derived from UARTCellularInterfae and provides hooks to
the target provided implementation of onbard_modem_api.h. An off-board modem, i.e, a modem on
a shield has to override the modem_init(), modem_power_up() etc as it cannot use
onboard_modem_api.h.
* Implements CellularInterface
* Reference design for CellularInterface implementations
* Uses an external mbed-os IP stack and talks to modem over PPP.
This provides a HAL layer for Modem bearing devices.
Provides a standard interface to upper layer drivers.
Platform providers will be implementing this API under their
specific targets.
As a reference, two implementations are provided under TARGET_C027 (UBLOX)
and TARGET_MTS_DRAGONFLY_F411RE (MultiTech).
targets.json now contains a tag "MODEM" which tells that this target
has a modem and the modem_api is protected by a flag DEVICE_MODEM
(following the DEVICE_SERIAL fashion ).
* Lays down ground for mbed modem_api
* Standardizes pin names relating to modem device for UBLOX C027 and MTS_DRAGONFLY_F411RE
devices
* Ublox modem api is changed to use a standard, platform independent name so that same
api could be used with multiple ubloc modems.
* DCD Polarity macro is added to assist the driver in knowing correct polarity
There is an easy default implementation of spi_master_block_write that
just calls spi_master_write in a loop, so the default implementation
of spi_master_block_write has been added to all targets.
Reworked the serial_format() function for STM32F0x
devices to take the format in the form:
data_bits - parity - stop_bits
E.g. 8 - N - 1
where data_bits exclude the parity bit.
Added a case for 7 bits data as at least the chips
STM32F0x1/STM32F0x2/STM32F0x8 support 7 bits data.
Consolidated serial_format() and uart_init()
functions into a general TARGET_STM serial_api.c
file since the functions are common to all STM targets.
Fixes#4189
F2 family also require that TIM_AUTORELOAD_PRELOAD_DISABLE is set,
otherwise the field could have undefined value from the stacj and may
lead to undefined behavior.
The error was found using USE_FULL_ASSERT HAL option.
Rather than adding F2 to the list of family, let's set this parameter for
any family where TIM_AUTORELOAD_PRELOAD_DISABLE applies.
When we want to activate USE_FULL_ASSERT macro in STM32 CUBE, there is a
need to have the assert map to MBED.
The easiest way to have this definition in a single place for all STM32
HAL and LL files using it, is to add a specific header file where the
porting to MBED is done.
There is an easy default implementation of spi_master_block_write that
just calls spi_master_write in a loop, so the default implementation
of spi_master_block_write has been added to all targets.
The STM32F3 cmsis_nvic code is currently checking for a specific flash
address when determining if the vector table is in flash or RAM. By
changing the test to instead see if the vector table base is NOT set to
the RAM address, it simplifies the code, and removes the dependency on
the flash vectors being located at a specific address. This becomes
important when adding a custom boot loader, which requires that the
flash vector table location in the mbed project be at a different
address.
Affected boards: NRF51_DK, NRF52_DK, Beetle. This change is temporary and
will be overwritten by RTX update. It's necessary for the boards to pass
updated tests.
According to @betzw, #3424 was put in for I2S with DMA. However, the latest I2S library now works without this patch.
The changes in DMA HAL for this potentially introduced corner case
scenarios. So it's best to revert the DMA changes.
Default timeout of 10ms was reported as an issue in #4300
There seems to be conditions or use cases where the system is loaded with
higher priority tasks so that SPI transfer would be delayed more than 10ms.
Recommendation from MBED team is to not implement any timeout at all as
there is no defined API in MBED to inform application of error cases.
Change the irq_handler parameter of NVIC_SetVector from a function
pointer to a uin32_t so it matches the cmsis specification. This
prevents the following problem from occurring in RTX5 when building
for IAR:
The error: Error[Pe167]: argument of type "void (*)(void)" is incompatible
with parameter of type "uint32_t".
If you are using Ethernet, and not SPI Arduino pins:
=> keep your board with the default configuration
If you are using SPI Arduino pins, and not Ethernet:
=> you should remove the JP6 bridge on the front side of the board
If you need SPI Arduino and Ethernet:
=> you have to patch the NUCLEO board on the back side: set solder bridge SB121 to off, and SB122 to on
=> D11 is no more connected to PA_7 but to PB_5
=> overwrite d11_configuration config value in json file
s140 headers renamed form ble_* to nrf_ble_*,
Removed s130 and s132 headers named form ble_*
(Them had been added by #2ff572682798562e812015dc775b5896e0fda5a4)
Headers inclusinons were changed in order to meet above changes.
Revrted bad change in us_ticker.c:
use __disable_irq lock instead of core_util_critical_section_enter lock
for setting rtc1 tick for systick emulation as was good before.
targets/targets.json already added MCU_LPC11U35_501 as an extra label
but it didn't have LPC11U35_501 (without the MCU_ prefix). Both of
these target names are used as folder names to organize files
specific to this device. For example the LPC11U35.ld linker script used
by GCC_ARM for this target is located in a TARGET_LPC11U35_501 folder.
I switched to using inheritance to properly setup the target labels
based on @theotherjimmy comments on PR #4252. Everything in the
XADOW_M0 targe appears to have been copy/pasted from LPC11U35_501
anyway so inheritance seems to be the best way to set the values of
the XADOW_M0 properties.
bcostm
TomoYamanaka
Cruz Monrreal
Vincent Coubard
jeromecoutant
Steven Cartmell
ccli8
Ashok Rao
Jimmy Brisson
Prashant Ravi
Andrzej Puzdrowski
Martin Kojtal
gorazd
Anna Bridge
Adam Heinrich
Dave Wu
Dexter Fryar
Kevin Bracey
Bilal
Maciej Rogozinski
Edmund Hsu
Przemyslaw Stekiel
Steven Cooreman
Boting Ren
Alessandro Angelino
andreas.larsson
Janne Kiiskilä
Mathieu Garivet
Mahadevan Mahesh
Tony Wu
Helmut Tschemernjak
Veijo Pesonen
Laurent MEUNIER
sarahmarshy
Michael Kaplan
Marko Fabo
cyliangtw
Steven Cooreman
Bartek Szatkowski
Bartosz Szatkowski
Marcus Chang
Yuguo Zou
danclement
Jammu Kekkonen
johnny
Andrea Corrado
Kevin Gilbert
amq
misodengaku
Piotr Grygorczuk
iotvietmember
maclobdell
Pavel Sorejs
Roberto Spelta
Pierre-Marie Ancele
adustm
Nabil Elqatib
Chris Snow
Seppe Stas
Russ Butler
mbedNoobNinja
Deepika
Russ Butler
Hasnain Virk
Jan Jongboom
Wolfgang Betz
mapellil
Ganesh Ramachandran
Rob Meades
Pavel Slama
MS30 CCChang12
toyowata
Tony Wu
jacobjohnson-ON
lordguilly
Jesse Marroquin
justinkim
mattot01
Bradley Scott
Brad Perry
arostm
Mike Fiore
Marc Moreno Berengue
Sam Grove
Andreas Larsson
Fahrzin Hemmati
Tamas Ban
gabker01
Tamas Kaman
Aksel Skauge Mellbye
kl-cruz
ianqianting
mickeyln
Francisco J. Manno
Christopher Haster
Shaun Nelson
Leon Lindenfelser
Russ Butler
Matthias L. Jugel
Dave Desrochers
Yoshihiro TSUBOI
Martin Kojtal
Brian Daniels
Michel Jaouen
justinkim
Adam Green