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5 Commits (784c473f63db474add90bc02841073c8ea8fdea0)

Author SHA1 Message Date
bcostm d0f8def2d7 F3 ST CUBE V1.9.0 2018-05-07 10:58:49 +02:00
Bradley Scott 7f12ad2a8c STM32F3: Correct handling of USB ISTR and endpoint registers 
The USB ISTR register consists of a mix of bits that are
write-zero-to-clear and read only bits.  As such, to clear a bit in
the ISTR, you should simply write the bitwise-NOT of the bit to clear.
Previously, the __HAL_PCD_CLEAR_FLAG() macro would do a bitwise-AND
with the ISTR register contents to clear a bit, but this could result
in another bit being inadvertently cleared if it is set by hardware
between the read and the write of the ISTR register.

Similarly, the USB endpoint registers have two bits that are
write-zero-to-clear, USB_EP_CTR_RX and USB_EP_CTR_TX, but the
PCD_CLEAR_RX_EP_CTR() and PCD_CLEAR_TX_EP_CTR() macros wrote back the
last read value for one of these bits when clearing the other bit.
This could result in inadvertent clearing of one of these bits if it
were set by the hardware between the read and the write.  These macros
have now both been adjusted to always write one to the bit not being
cleared to prevent inadvertent clears.
 2017-04-26 10:23:02 -04:00
Laurent MEUNIER 9640936714 F3 CUBE update V1.7.0 
CMSIS v2.3.0 => v2.3.1
    HAL   v1.3.0 => v1.4.0
    LL    v1.4.0
 2017-01-23 16:44:21 +01:00
Michel Jaouen 182c311fbd TARGET_STM : USB FS STM HAL changes 2016-11-09 12:08:45 +01:00
Christopher Haster 26ced98734 restructure - Restructured cmsis directory 
targets/cmsis -> cmsis
targets/cmsis/TARGET_* -> targets/TARGET_*/device
targets/cmsis/TARGET_*/mbed_rtx.h -> targets/TARGET_*/mbed_rtx.h
 2016-10-04 17:51:44 -05:00