The IRQ disable was always disabling both rising
and falling edges of the interrupt thereby causing
failures in cases when one of the two should stay enabled.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Update the clock divider setting
2. ADC resolution is 12-bits, update the API return value
to return 16-bit result
3. Update IOMUX setup
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
An extra start signal was observed on the bus which was
discovered by the FPGA test shield.
This is because the hardware sends out a transaction as soon
as a write to the START bit. Hence the write to the START
bit is delayed by using a flag.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
As the build tool in mbed-os 5.13 cannot appropriately deal with a segmented
bootloader when combining it with an application, this commit adjusts the
size reserved for interrupts (via the linker file) to avoid a bootloader
segmentation due to an unpopulated ROM area.
The microcontroller has a total of 60 vector interrupts + 16 exception
handlers. The allocated ROM flash for interrupts should be (60 + 16) x word
size in bytes = 76 x 4 = 304 = 0x130.
This commit changes the interrupt reserved space from 0x140 to 0x130.
The file 'fsl_powerquad_data.h' declares several dctXXX_cosFactor
arrays with sizes twice larger compared to the actual definitions in
'fsl_powerquad_data.c'.
Reimplement atomic code in inline assembly. This can improve
optimisation, and avoids potential architectural problems with using
LDREX/STREX intrinsics.
API further extended:
* Bitwise operations (fetch_and/fetch_or/fetch_xor)
* fetch_add and fetch_sub (like incr/decr, but returning old value -
aligning with C++11)
* compare_exchange_weak
* Explicit memory order specification
* Basic freestanding template overloads for C++
This gives our existing C implementation essentially all the functionality
needed by C++11.
An actual Atomic<T> template based upon these C functions could follow.
Spotted in compiler warnings - code was trying to access a non-existent
second security control block, rather than access the settings for the
second APB bridge in the first and only security control block.
Fixes test failure seen with tests-mbed_hal-stack_size_unification
under IAR and ARM toolchain
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Since commit 12c6b1bd8, the i.MX RT1050 has effectively had its data
cache disabled, as the SDRAM was marked Shareable; for the Cortex-M7,
shareable memory is not cached.
This was done to make the Ethernet driver work without any cache
maintenance code. This commit adds cache maintenance and memory barriers
to the Ethernet driver, and removes the Shareable attribute from the
SDRAM, so the data cache is used again.
Cache code in the base fsl_enet.c driver has not been activated - the
bulk of it is in higher-level Read and Write calls that we're not using,
and there is one flawed invalidate in its initialisation. Instead
imx_emac.cpp takes full cache responsibility.
This commit also marks the SDRAM as read/write-allocate. As the
Cortex-M7 has its "Dynamic read allocate mode" to automatically switch
back to read-allocate in cases where write allocate is working poorly
(eg large memset), this should result in a performance boost with no
downside.
Activating write-allocate is also an attempt to provoke any flaws in
cache maintenance - the Ethernet transmit buffers for example will be
more likely to have a little data in the cache that needs cleaning.
The flash driver for the LPC55S69 is different from
prior LPC family. Move the Flash HAL driver to SoC
specific folder
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Seppo Takalo
Mahesh Mahadevan
Arto Kinnunen
Martin Kojtal
Hugues Kamba
Mathias Brossard
Kevin Bracey
Michael Schwarcz
David Saada
Oren Cohen
Alexander Zilberkant
deepikabhavnani