Commit Graph

356 Commits (6b8bde9471d696696b53ce438ca9d6b69c2042da)

Author SHA1 Message Date
Martin Kojtal 967b45a3ec Merge pull request #2029 from adustm/b_fix_MBED_16_STM32F4
Fix #2027 Add timeinfo.tm_isdst = -1 to pass MBED_16 test with IAR.
2016-07-11 11:07:40 +01:00
Bogdan Marinescu 2d41d9b013 Merge pull request #2138 from ohagendorf/progen_correction
[target.json - progen] changing a wrong config
2016-07-11 12:54:22 +03:00
Martin Kojtal 8188684cab Merge pull request #2136 from lrks/fix_i2c_slave_addr_ksdk2
[KSDK2_MCUS] Fix I2C slave address
2016-07-11 09:50:57 +01:00
ohagendorf 7388b446d4 [target.json - progen] changing a wrong config
ARCH_MAX has a STM32F407 mcu
2016-07-10 20:58:35 +02:00
lrks 4b77054940 Fix I2C slave address
Remove the needless bit shift for I2C slave address.
2016-07-10 10:34:13 +09:00
Christopher Haster 98d55e71d8 Moved core_util_atomic_*_ptr functions out of cortex switch 2016-07-09 11:14:16 -05:00
Christopher Haster 70013d03b6 Fixed casts around calls to atomic u32 functions
- uint32_t -> void *
- void ** -> uint32_t *

For whatever reason `uintptr_t` and `uint32_t` expand to incompatible
types `unsigned int` and `unsigned long int`. This is implicitely casted
when passed by value, but causes a warning in gcc and error in iar when
passed by pointer.

This issue is not present on x86_32 gcc
2016-07-09 11:13:20 -05:00
Christopher Haster 2c78dca69c Fixed typo in incr/decr function
Result of last minute change, interestingly only emits a
warning in gcc.
2016-07-07 22:51:31 -05:00
Sam Grove c55c07a890 Merge pull request #2054 from geky/critical-cas-ptr
Added cas instrinsics for pointer values
2016-07-07 16:59:56 -05:00
Christopher Haster 946199183c Minor documentation updates for critical
- extra dereference in cas example
- clarification of incr/decr
2016-07-06 13:06:37 -05:00
Christopher Haster 9067148618 Standardized style of critical.h
per @0xc0170
2016-07-06 13:06:37 -05:00
Christopher Haster 26726cc170 Added proper usage of standard types for critical pointer functions 2016-07-06 13:06:34 -05:00
Christopher Haster cf6f8e33fb Added cas instrinsics for pointer values
- core_util_atomic_cas
- core_util_atomic_incr
- core_util_atomic_decr
2016-07-06 13:04:36 -05:00
Martin Kojtal 704c042707 Merge pull request #2109 from 0xc0170/dev_lpc2368_arm
Targets - LPC23678 ARM fails to build, remove from supported toolchains
2016-07-06 11:40:14 +01:00
Bogdan Marinescu 087b8fa648 Added proper definition for NRF51_MICROBIT_B 2016-07-06 12:31:30 +03:00
0xc0170 668dd17784 Targets - LPC23678 ARM fails to build, remove from supported toolchains
Tracking issue: https://github.com/mbedmicro/mbed/issues/2108
2016-07-06 09:41:32 +01:00
Martin Kojtal 7c00a75b05 Merge pull request #2105 from bridadan/ignore-target-specific-test
Adding .mbedignore for target specific test
2016-07-06 09:05:49 +01:00
Martin Kojtal 8d1024433a Merge pull request #2096 from 0xc0170/fix_release_targets
Fix release targets in the build_release.py
2016-07-06 09:02:44 +01:00
Brian Daniels af7da146a9 Adding .mbedignore for target specific test 2016-07-05 11:05:57 -05:00
Michel Jaouen 1794463a06 [STM32F3]: fix for uart baudrate. 2016-07-05 14:30:25 +01:00
Martin Kojtal 17693ac0fa Merge pull request #2100 from jamike/fix_NUCLEO_F303K8_MBED_16
[NUCLEO_F303K8] fix MBED_16.
2016-07-05 13:30:39 +01:00
0xc0170 de4c97abb8 Targets - add release boolean flag 2016-07-05 10:47:51 +01:00
Michel JAOUEN 552631ec9e [NUCLEO_F303K8] fix MBED_16.
RTC clk on LSI (no LSE connected)
2016-07-05 11:45:12 +02:00
Michel JAOUEN e04fab1069 [DISCO_F303VC] : fix build issue 2016-07-05 11:23:42 +02:00
Martin Kojtal e56b9d06b7 Merge pull request #2087 from ohagendorf/stm32f7xx_fpu_sp_dp
fpu with single/double precision - bugfix and extension
2016-07-05 09:39:44 +01:00
Martin Kojtal fe3b80aa68 Merge pull request #2090 from jamike/fix#2089
Fix#2089
2016-07-05 08:36:13 +01:00
Olaf Hagendorf 78bb74a761 fpu with single/double precision - rebasing
- master branch got two new cortex-m4f targets -> travis build failed
2016-07-04 22:10:49 +02:00
Olaf Hagendorf 4fe41d4edd fpu with single/double precision - removing redundancy
- removing redundancy as discussed in PR #2087:
 - in target.json the core option can have only this values : "Cortex-M0", "Cortex-M0+", "Cortex-M1", "Cortex-M3", "Cortex-M4", "Cortex-M7", "Cortex-A9" - Cortex-M4F and Cortex-M7F removed
 - in target.json an additional fpu option with values: "single" and "double" can be used
- build and export scripts are changed to handle this

- tested (compiling, running on hardware) with nucleo_f767 (cortex-m7 with double precision fpu), nucleo_f746 (cortex-m7 with single precision fpu), nucleo_f446 and nucleo_l467 (cortex-m4 with single precision fpu), teensy31 (cortex-m4 without fpu - only build test), nucleo_l073 (cortex-m0)
- singletest results are added to PR #2087 comments
2016-07-04 22:08:31 +02:00
Olaf Hagendorf ea196e2adb fpu with single/double precision - bugfix and extension
- creating new core name Cortex_M7F_DP for a target with a double precision fpu
- adding new core name to arm.py to set compiler/linker flags to a double precision fpu when configured in target.json
- up to now: gcc wrote flag for a double precision fpu -> target with STM32F746 didn't run when using double variables - mcu has only single precision fpu
- changing gcc.py to use single precision for Cortex-M7 und double precision for Cortex_M7F_DP

tested with NUCLEO_F746, NUCLEO_F767 and build.py+make.py and exporting with project.py + compiling/flashing

- iar.py need a similar extention - I didn't change that yet because
  - did not run at the moment - python exception
  - currently worked on in PR #1948
2016-07-04 22:08:30 +02:00
Erwan GOURIOU eaf77ed37f [STM32F4xx][NUCLEO_F429ZI] Add on for NUCLEO_F429ZI export and tests 2016-07-04 15:20:12 +02:00
Erwan Gouriou 091e62cbf7 [STM32F4xx][NUCLEO_F429ZI] Update PeripheralPins.c and pin definition 2016-07-04 14:00:41 +02:00
Erwan Gouriou 9bb08291ce [STM32F4xx] Add support for NUCLEO_F429ZI 2016-07-04 14:00:41 +02:00
Martin Kojtal 2b5f0317c4 Merge pull request #2039 from LMESTM/dev_NUCLEO_F446ZE
Add nucleo_f446ze
2016-07-04 11:49:15 +01:00
Martin Kojtal 4c0319388b Merge pull request #2086 from svastm/fix_mbed_23_l0
[STM32L0XX] Remove stabilization of the timer
2016-07-04 11:44:51 +01:00
Martin Kojtal 5af16c9546 Merge pull request #2079 from fvincenzo/master
[BEETLE] Add BLE support
2016-07-04 11:01:27 +01:00
Laurent Meunier 39197e6ad3 [NUCLEO_F446ZE] Add HAL target
Inspired from NUCLEO_F446RE, only PinNames.h updated according to NUCLEO_F446ZE schematics.
2016-07-04 11:42:43 +02:00
Laurent Meunier d6e7df9591 [NUCLEO_F446ZE] Add CMSIS target
Adding new nucleo target, actually exactly the same as NUCLEO_F446RE
2016-07-04 11:42:43 +02:00
Martin Kojtal ebfe44c1bf Merge pull request #2038 from infinnovation/parityeven-fix
[K64F] serial_api.c: Fix #1979 assertion error for ParityEven
2016-07-04 10:40:06 +01:00
Martin Kojtal a3a4c78ea0 Merge pull request #2070 from akselsm/efm32-update
[EFM32] Update HAL implementation
2016-07-04 10:35:58 +01:00
Martin Kojtal 1216d8088d Merge pull request #2092 from akselsm/spi-init-fix
SPI: Properly aquire peripheral in constructor
2016-07-04 10:10:11 +01:00
Aksel Skauge Mellbye a81fdc461d [EFM32] Backport changes from mbed OS 3. 2016-07-04 10:08:20 +02:00
Aksel Skauge Mellbye da2a4ccbae [EFM32] Add SPI test. Refactor SPI HAL, fix misc test failures.
Properly support the bit_width parameter for the async API.
Fix issues with long DMA transfers (exceeding 1023 frames).
2016-07-04 10:08:09 +02:00
Steven Cooreman 746c485b43 [EFM32] Swap out INT_* functions with mbed critical sections 2016-07-04 10:06:32 +02:00
Aksel Skauge Mellbye 641087ce65 [EFM32] Add delay after reset for greentea test runs.
The host-test resets the target by sending a UART break. After this, it takes some
time for the target to come back up. Without this timeout, the __sync packet
sent by greentea would not be retransmitted by the interface chip (i.e. it would never
reach the target). Testing on different devices indicates that 2 seconds delay
is sufficient for the device to reset and the  __sync packet to reach the target.
2016-07-04 10:03:02 +02:00
Aksel Skauge Mellbye b09a87ffb8 SPI: Properly aquire peripheral in constructor
Prevent mismatch between _owner and peripheral configuration. In the previous
implementation, the following code would leave the peripheral in an inconsistent
state:

```
SPI spi1(...);      // _owner is NULL, peripheral config is 1
spi1.transfer(...); // _owner is 1, config is 1
SPI spi2(...);      // _owner is 1, config is 2
spi1.transfer(...)  // 1 thinks it still owns peripheral, doesn't reconfigure
```
2016-07-04 09:52:57 +02:00
Michel Jaouen 680afcb677 [STM32F3]: fix iar built (cast error) 2016-07-03 23:46:29 +02:00
Vincenzo Frascino 3785de8412 [BEETLE] Add BLE Cordio Support into HAL
This patch adds BLE Cordio support into MBED HAL. It contains:
* Cordio and TRIM object files
* The Cordio stack header file
* The Cordio library for Beetle Systems precompiled for GCC and ARMCC

The BLE implementation will be provided in a future patch in the mbed-os
repository.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
2016-07-01 17:25:11 +01:00
Vincenzo Frascino 1be4788b1a [BEETLE] Mbed SDK Init Update
In Beetle systems eFlash and Cache Flash are always enabled by default.
This patch updates the Mbed SDK Init procedure to reflect the changes in
the eFlash and Cache Flash Drivers provided in a previous patch.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
2016-07-01 17:24:14 +01:00
Vincenzo Frascino 15745a063d [BEETLE] Add BLE Cordio support into CMSIS
This patch adds BLE Cordio support into CMSIS. It provides:
* A modification for the linker scripts for both ARMCC and GCC
  compilers that adds the cordio specific sections.
* A method to access the Flash stored MAC Address.

The CORDIO_RO_2.1.o and TRIM_2.1.o objects that rappresent the Cordio
firmware will be added by a future patch.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
2016-07-01 17:23:48 +01:00
Vincenzo Frascino 55216f1245 [BEETLE] eFlash and Flash Cache Interface refinement
In Beetle systems eFlash and Cache Flash are always enabled by default.
This patch refines the interface of these drivers to match the
functionalities exposed by the platform.

This patch renames also writel/readl in these drivers to uppercase to follow
acros code convention.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
2016-07-01 17:23:20 +01:00