Commit Graph

6582 Commits (61c63b3789e1e2d8c4e4bacd2577a8ba57a79d8f)

Author SHA1 Message Date
0xc0170 de4c97abb8 Targets - add release boolean flag 2016-07-05 10:47:51 +01:00
Michel JAOUEN 552631ec9e [NUCLEO_F303K8] fix MBED_16.
RTC clk on LSI (no LSE connected)
2016-07-05 11:45:12 +02:00
Michel JAOUEN e04fab1069 [DISCO_F303VC] : fix build issue 2016-07-05 11:23:42 +02:00
Martin Kojtal e56b9d06b7 Merge pull request #2087 from ohagendorf/stm32f7xx_fpu_sp_dp
fpu with single/double precision - bugfix and extension
2016-07-05 09:39:44 +01:00
Martin Kojtal fe3b80aa68 Merge pull request #2090 from jamike/fix#2089
Fix#2089
2016-07-05 08:36:13 +01:00
Olaf Hagendorf 78bb74a761 fpu with single/double precision - rebasing
- master branch got two new cortex-m4f targets -> travis build failed
2016-07-04 22:10:49 +02:00
Olaf Hagendorf 4fe41d4edd fpu with single/double precision - removing redundancy
- removing redundancy as discussed in PR #2087:
 - in target.json the core option can have only this values : "Cortex-M0", "Cortex-M0+", "Cortex-M1", "Cortex-M3", "Cortex-M4", "Cortex-M7", "Cortex-A9" - Cortex-M4F and Cortex-M7F removed
 - in target.json an additional fpu option with values: "single" and "double" can be used
- build and export scripts are changed to handle this

- tested (compiling, running on hardware) with nucleo_f767 (cortex-m7 with double precision fpu), nucleo_f746 (cortex-m7 with single precision fpu), nucleo_f446 and nucleo_l467 (cortex-m4 with single precision fpu), teensy31 (cortex-m4 without fpu - only build test), nucleo_l073 (cortex-m0)
- singletest results are added to PR #2087 comments
2016-07-04 22:08:31 +02:00
Olaf Hagendorf ea196e2adb fpu with single/double precision - bugfix and extension
- creating new core name Cortex_M7F_DP for a target with a double precision fpu
- adding new core name to arm.py to set compiler/linker flags to a double precision fpu when configured in target.json
- up to now: gcc wrote flag for a double precision fpu -> target with STM32F746 didn't run when using double variables - mcu has only single precision fpu
- changing gcc.py to use single precision for Cortex-M7 und double precision for Cortex_M7F_DP

tested with NUCLEO_F746, NUCLEO_F767 and build.py+make.py and exporting with project.py + compiling/flashing

- iar.py need a similar extention - I didn't change that yet because
  - did not run at the moment - python exception
  - currently worked on in PR #1948
2016-07-04 22:08:30 +02:00
Martin Kojtal c034f48c26 Merge pull request #2077 from egostm/dev_NUCLEO_F429ZI
Add support for Nucleo F429ZI
2016-07-04 15:00:50 +01:00
Marcelo Salazar 99471ec1ee Install correct version of tools 2016-07-04 14:20:24 +01:00
Erwan GOURIOU eaf77ed37f [STM32F4xx][NUCLEO_F429ZI] Add on for NUCLEO_F429ZI export and tests 2016-07-04 15:20:12 +02:00
Erwan Gouriou 091e62cbf7 [STM32F4xx][NUCLEO_F429ZI] Update PeripheralPins.c and pin definition 2016-07-04 14:00:41 +02:00
Erwan Gouriou 9bb08291ce [STM32F4xx] Add support for NUCLEO_F429ZI 2016-07-04 14:00:41 +02:00
Martin Kojtal 2b5f0317c4 Merge pull request #2039 from LMESTM/dev_NUCLEO_F446ZE
Add nucleo_f446ze
2016-07-04 11:49:15 +01:00
Martin Kojtal 4c0319388b Merge pull request #2086 from svastm/fix_mbed_23_l0
[STM32L0XX] Remove stabilization of the timer
2016-07-04 11:44:51 +01:00
Martin Kojtal 5af16c9546 Merge pull request #2079 from fvincenzo/master
[BEETLE] Add BLE support
2016-07-04 11:01:27 +01:00
Laurent Meunier 6671e1abc8 [NUCLEO_F446ZE] Tests update 2016-07-04 11:47:06 +02:00
Laurent Meunier be889fc49b [NUCLEO_F446ZE] Add RTOS support 2016-07-04 11:47:06 +02:00
Laurent Meunier 4e1a3351b2 [NUCLEO_F446ZE] Add to build and export scripts 2016-07-04 11:44:28 +02:00
Laurent Meunier 39197e6ad3 [NUCLEO_F446ZE] Add HAL target
Inspired from NUCLEO_F446RE, only PinNames.h updated according to NUCLEO_F446ZE schematics.
2016-07-04 11:42:43 +02:00
Laurent Meunier d6e7df9591 [NUCLEO_F446ZE] Add CMSIS target
Adding new nucleo target, actually exactly the same as NUCLEO_F446RE
2016-07-04 11:42:43 +02:00
Martin Kojtal ebfe44c1bf Merge pull request #2038 from infinnovation/parityeven-fix
[K64F] serial_api.c: Fix #1979 assertion error for ParityEven
2016-07-04 10:40:06 +01:00
Martin Kojtal a3a4c78ea0 Merge pull request #2070 from akselsm/efm32-update
[EFM32] Update HAL implementation
2016-07-04 10:35:58 +01:00
Martin Kojtal 1216d8088d Merge pull request #2092 from akselsm/spi-init-fix
SPI: Properly aquire peripheral in constructor
2016-07-04 10:10:11 +01:00
0xc0170 b29e9d093f Merge branch 'bridadan-fix-lpc1768-test-compile' 2016-07-04 09:11:09 +01:00
Brian Daniels 529da7c43e Tests - use MBED_ALIGN instead of specific compiler attributes
This fixes the build of vector realloc test for all compilers
2016-07-04 09:10:19 +01:00
Aksel Skauge Mellbye a81fdc461d [EFM32] Backport changes from mbed OS 3. 2016-07-04 10:08:20 +02:00
Aksel Skauge Mellbye da2a4ccbae [EFM32] Add SPI test. Refactor SPI HAL, fix misc test failures.
Properly support the bit_width parameter for the async API.
Fix issues with long DMA transfers (exceeding 1023 frames).
2016-07-04 10:08:09 +02:00
Steven Cooreman 746c485b43 [EFM32] Swap out INT_* functions with mbed critical sections 2016-07-04 10:06:32 +02:00
Aksel Skauge Mellbye 641087ce65 [EFM32] Add delay after reset for greentea test runs.
The host-test resets the target by sending a UART break. After this, it takes some
time for the target to come back up. Without this timeout, the __sync packet
sent by greentea would not be retransmitted by the interface chip (i.e. it would never
reach the target). Testing on different devices indicates that 2 seconds delay
is sufficient for the device to reset and the  __sync packet to reach the target.
2016-07-04 10:03:02 +02:00
Aksel Skauge Mellbye b09a87ffb8 SPI: Properly aquire peripheral in constructor
Prevent mismatch between _owner and peripheral configuration. In the previous
implementation, the following code would leave the peripheral in an inconsistent
state:

```
SPI spi1(...);      // _owner is NULL, peripheral config is 1
spi1.transfer(...); // _owner is 1, config is 1
SPI spi2(...);      // _owner is 1, config is 2
spi1.transfer(...)  // 1 thinks it still owns peripheral, doesn't reconfigure
```
2016-07-04 09:52:57 +02:00
Michel JAOUEN b73fd5e6f9 Fix issue #2089 :IAR set_main_stack
i.e test RTOS_4 on NUCLEO_F303K8 with IAR fails.
(rt_stk_check detects that main_stack Magic is corrupted)
2016-07-03 23:47:08 +02:00
Michel Jaouen 680afcb677 [STM32F3]: fix iar built (cast error) 2016-07-03 23:46:29 +02:00
Vincenzo Frascino 3785de8412 [BEETLE] Add BLE Cordio Support into HAL
This patch adds BLE Cordio support into MBED HAL. It contains:
* Cordio and TRIM object files
* The Cordio stack header file
* The Cordio library for Beetle Systems precompiled for GCC and ARMCC

The BLE implementation will be provided in a future patch in the mbed-os
repository.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
2016-07-01 17:25:11 +01:00
Vincenzo Frascino 1be4788b1a [BEETLE] Mbed SDK Init Update
In Beetle systems eFlash and Cache Flash are always enabled by default.
This patch updates the Mbed SDK Init procedure to reflect the changes in
the eFlash and Cache Flash Drivers provided in a previous patch.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
2016-07-01 17:24:14 +01:00
Vincenzo Frascino 15745a063d [BEETLE] Add BLE Cordio support into CMSIS
This patch adds BLE Cordio support into CMSIS. It provides:
* A modification for the linker scripts for both ARMCC and GCC
  compilers that adds the cordio specific sections.
* A method to access the Flash stored MAC Address.

The CORDIO_RO_2.1.o and TRIM_2.1.o objects that rappresent the Cordio
firmware will be added by a future patch.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
2016-07-01 17:23:48 +01:00
Vincenzo Frascino 55216f1245 [BEETLE] eFlash and Flash Cache Interface refinement
In Beetle systems eFlash and Cache Flash are always enabled by default.
This patch refines the interface of these drivers to match the
functionalities exposed by the platform.

This patch renames also writel/readl in these drivers to uppercase to follow
acros code convention.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
2016-07-01 17:23:20 +01:00
Martin Kojtal ce830296d0 Merge pull request #1909 from ohagendorf/stm32f7cube_2
[STM32F7xx] update cube hal to v1.4, adding NUCLEO_F767
2016-07-01 17:10:41 +02:00
Martin Kojtal 6e103c3e13 Merge pull request #1883 from adbridge/master
Update function get_interrupts_disabled() to return a bool value rather
2016-07-01 17:10:22 +02:00
Olaf Hagendorf 4211f7581e [NUCLEO_F7xx] adding F767 to build_release and adding default_build to target.json 2016-07-01 16:27:20 +02:00
svastm a9b3b9cce9 [STM32L0XX] Remove stabilization of the timer 2016-07-01 16:10:52 +02:00
Anna Bridge 329f8a10dc Add core_util_ prefix to are_interrupts_enabled() function.
For consistency with other exposed functions from this file, core_util_
prefix should be added.
2016-07-01 15:08:31 +01:00
Anna Bridge 2292794385 Reverse the logic to get_interrupts_disabled() to are_interrupts_enabled()
and update the using functions accordingly.

Usage:
bool interrupts_enabled = are_interrupts_enabled()

Remove superfluos shift in are_interrupts_enabled().
2016-07-01 14:55:53 +01:00
Anna Bridge 9f052bc500 Update function get_interrupts_disabled() to return a bool value rather
than an integer. This removes the need for all users to mask the returned
value with 0x1 to determine interrupt status.
Expose this function externally to allow other users to check interrupt
status in a manner which will work for both cortex-A and cortex-M .
Usage:
bool disabled = get_interrupts_disabled();
2016-07-01 14:53:53 +01:00
ohagendorf fdda915a8a [NUCLEO_F767ZI] adding target to rtos lib 2016-07-01 15:19:30 +02:00
ohagendorf 6b6371420c [NUCLEO_F767ZI] adding IAR toolchain 2016-07-01 15:17:29 +02:00
ohagendorf 23f4152759 [NUCLEO_F767] removing not longer necessary uvision5 options 2016-07-01 15:17:28 +02:00
ohagendorf 956b733d0f [STM32F676] correcting memory sizes for gcc_arm 2016-07-01 15:17:27 +02:00
ohagendorf 40506d899b rebase failure 2016-07-01 15:17:27 +02:00
ohagendorf 8292dd2fd2 Add call to SystemCoreClockUpdate() and Reset peripheral before init …
…phase.

patch from bcostm
2016-07-01 15:17:26 +02:00