Align with mainline BSP and fix relevant bugs:
1. Align with SPI module naming
(1) Remove SPI5
(2) Degrade QSPI0 to SPI4 so that it can use for standard SPI
2. Fix some code lacking GPIO H
3. Implement __PC(...) by following BSP instead of with MBED_CALLER_ADDR()
4. Add SCU_IRQHandler(). Change printf(...) with interrupt-safe error(...)
5. Other minor alignment change
The existing logic was insufficient to properly handle odd and even
parity setting, e.g. serial_getc() returned 9-bit data for 8O1
transmission format.
1. Do not disable and enable osillators during deep sleep
entry and exit
2. Increase the deep sleep to pass tests
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
It is required by Mbed HAL API to generate TxIrq interrupt when TXD register is empty (also after enabling TxIrq interrupt):
f73a62afbf/hal/serial_api.h (L144-L147)
The driver uses DMA to perform uart transfer and TxIrq is generated after the transfer is finished.
While enabling TxIrq we will check if TXD reg is empty and manually trigger the interrupt.
1. Re-organize to make clear for all targets/toolchains support in single startup file
2. Inline assembly syntax is limited, esp. on IAR. Try paving the way for accessing external symbols still in inline assembly instead of re-write in assembly.
1. Enable GCC support on non-secure targets
2. Disable GCC support on secure targets becasue of GCC bug (as of 9-2019-q4-major): In non-secure entry function, callee-saved registers must be restored, but they are incorrectly cleared at optimization level "Os".
In STM32 Cube HAL, in interrupt mode (async),
2 bytes can be prepared in hardware registers without any read
(1 in regular register, the other in shift register),
but Only 1 RX byte can stored in hardware register, specially when there is no hardware FIFO.
If interrupt handling is fast enough, each read is made in parralele of the write.
But if interrupt handling is too long or is interrupted for too long,
it can happen that one read byte is lost (overrun).
For STM32F4, Tickless has been deactivated to avoid such issue.
For STM32L0, we don't want to deactivate tickless,
because those chips are specially design for lowpower.
So instead of removing SPI async mode,
we propose to change the HAL behavior specially for L0:
each byte is send only when previous read is performed.
Thus only 1 RX byte at a time which is saved in hardware register.
This prevent overrun, but it introduceS some latency between each byte send,
this is why it is not applied to all STM32 families.
Dustin Crossman
Martin Kojtal
Chun-Chieh Li
midd
jeromecoutant
thegecko
Gabor Abonyi
Przemyslaw Stekiel
Filip Jagodzinski
Mahesh Mahadevan
Marcelo Salazar
Hugues Kamba
Alexandre Bourdiol