9 Commits (500221c6a0cdd6f79e4a8505ac5cad59eb191b2f)

Author	SHA1	Message	Date
Kevin Bracey	00c9005b4e	[CMSIS_5]: Updated to ca812421	2019-04-10 14:41:35 +03:00
Kevin Bracey	91f0be6ac3	Check correct ARMC6 predefine for FP codegen ... For ARMC6, CMSIS headers were checking the `__ARM_PCS_VFP`, which indicates hardfp ABI in use, when they need to check whether FP code generation is enabled. Change this to `__ARM_FP`, so it works for platforms using softfp ABI. Change already present in CMSIS_5 repo, via commit 969822ae162539d50617d1e5a3634ee2fd3b60f6, but redone with local search-and-replace.	2018-12-19 13:03:11 +02:00
Russ Butler	342841aa0f	[CMSIS_5]: Updated to 0b521765	2018-08-25 20:41:00 -05:00
Bartek Szatkowski	8afbd66763	[CMSIS_5]: Updated to 49ac527a	2018-05-14 12:18:20 +01:00
Jonatan Antoni	063717d90d	Core(A): Changed macro __DEPRECATED to CMSIS_DEPRECATED. (Issue #287) ... __DEPRECATED conflicts with a predefined macro in GCC C++ mode.	2017-12-21 14:09:25 +09:00
Jonatan Antoni	2f06202a9b	Core(A): Refactored L1 Cache maintenance to be compiler agnostic. ... - Added L1 Cache test cases to CoreValidation. - Adopted FVP Cortex-A configs to simulate cache states.	2017-12-21 14:09:25 +09:00
TomoYamanaka	11ec7a2209	CMSIS-Core(A): Add MMU section_normal_nc macro ... I added the macro definition for non-cache area.	2017-12-21 14:09:25 +09:00
Daniel Brondani	0c1961a724	CMSIS-Core(A): Fixed enumerated type increment in GIC_DistInit and GIC_CPUInterfaceInit functions	2017-12-21 14:09:25 +09:00
Bartek Szatkowski	a03591d6e3	CMSIS/RTX: Update CMSIS and RTX to 22b68c ... This includes Cortex A support and directory reshuffle.	2017-11-01 09:25:42 +00:00