As per the IAR Development guide, below options for CPU are valid
1. Cortex-M33
2. Cortex-M33.no_dsp (core without integer DSP extension)
3. Cortex-M33.fp (floating-point unit with support for single precision)
4. Cortex-M33.no_se (core without support for TrustZone)
5. Cortex-M4
6. Cortex-M4F
7. Cortex-M7
8. Cortex-M7.fp.dp (floating-point unit with support for double precision)
9. Cortex-M7.fp.sp (floating-point unit with support for single precision)
Below are the options read from the toolchains/arm
armclang --target=arm-arm-none-eabi -mcpu=list
The following arguments to option 'mcpu' can be selected:
-mcpu=cortex-m0
-mcpu=cortex-m0plus
-mcpu=cortex-m1
-mcpu=cortex-m3
-mcpu=cortex-m4
-mcpu=cortex-m7
-mcpu=cortex-m23
-mcpu=cortex-m33
...
armlink --cpu=list
The following arguments to option 'cpu' can be selected:
--cpu=Cortex-M0
--cpu=Cortex-M0plus
--cpu=Cortex-M1
--cpu=Cortex-M1.os_extension
--cpu=Cortex-M1.no_os_extension
--cpu=Cortex-M4
--cpu=Cortex-M4.no_fp
--cpu=Cortex-M7
--cpu=Cortex-M7.fp.sp
--cpu=Cortex-M7.no_fp
--cpu=Cortex-M23
--cpu=Cortex-M33
--cpu=Cortex-M33.no_fp
--cpu=Cortex-M33.no_dsp
--cpu=Cortex-M33.no_dsp.no_fp
...
armclang --target=arm-arm-none-eabi -mfpu=list
The following arguments to option 'mfpu' can be selected:
-mfpu=fpv4-sp-d16
-mfpu=fpv5-sp-d16
-mfpu=fpv5-d16
...
For binary compatibility with ARMC5, use the hard ABI variant whenever
we have FP hardware - this is ARMC5's default behaviour, which we do not
override.
Cortex-M4F was already using hard; this brings M7F and M33F into line.
### Description
PR #8607 will cause problems for the NRF52832 and the NRF52840
in the online compiler starting with 5.10.2. This PR prevents this problem
by using a toggle in `targets.json` to enable these new defines for every
target except for the NRF52832 and NRF52840.
### Pull request type
[x] Fix
[ ] Refactor
[ ] Target update
[ ] Functionality change
[ ] Docs update
[ ] Test update
[ ] Breaking change
### Description
This PR moves the old memap file handling required for differential
memap from within memap to the toolchain object. This has the
advantage that we can do the `mv <app>.map <app>.map.old` the moment
before it is overwritten by the linker. This should allow multiple
reruns of memap without modifying your build directory.
### Pull request type
[ ] Fix
[x] Refactor
[ ] Target update
[ ] Functionality change
[ ] Docs update
[ ] Test update
[ ] Breaking change
The 'archive' method of the toolchain class 'ARM' expects that self.ar
is a string, but the constructor of the class 'ARMC6' initializes it
with a list. This patch fixes the issue.
Moved "bootloader_not_supported" check to where it was and handle that exception at only one place.
Removed ram/rom size info for realtek from targets.json. THe info we have is not correct.
was Not handling config exceptions from regions and ram_regions property
adding rom-ram info for REALTEK_RTL8195AM
1. Adding SRAM in available ram
2. If the target doesn't exist in cmsis but targets.json, handle accordingly and raise apt exceptions where needed.
3. If no sram is provided, raise exception
### Description
The prior fix made the assumption that you wanted to compute all of the
parents for a give header file going all the way up the path. This is
not true: you probably want to stop when the project stops. We already
keep track of a virtual name within the project, so instead, we compute
parents of the name, and generate the actual location of these files in
your FS as the path. This makes the solution robust offline and online
(I tested it with my local copy of os.mbed.com)
### Pull request type
[x] Fix
[ ] Refactor
[ ] Target update
[ ] Functionality change
[ ] Docs update
[ ] Test update
[ ] Breaking change
RAM/ROM memory data of target is required for statistics and linker
files, goal here is to fetch maximum 4 RAM/ROM regions from CMSIS pack
and make them available for C/C++/Linker flags as defines
1. In drivers/Timer.cpp make sure that hardware timer is initialized outside of critical section.
This is because on PSoC 6 hardware resources are shared between both cores
and we have to make sure that the other core is not already using a particular resource.
This mechanism is based on interprocessor communication taht cannot be handled iside of
critical section.
2. Added support for post-binary hook function for PSoC 6 targets, so the hex image for M0+ CPU core
can be merged with M4 core image for the final image.
3. Added possibility to use hook function from exportes, so the M0+ hex image could be included
in the generated project.
4. Included hex images in the build dependency list, so the update of image is catched by the
build process.
Martin Kojtal
Deepika
Brian Daniels
Cruz Monrreal
Kevin Bracey
Senthil Ramakrishnan
Mahesh Mahadevan
Anna Bridge
Jimmy Brisson
Oren Cohen
Mikhail Maltsev
Aashish chaddha
jeromecoutant
Leszek Rusinowicz
Mo Chen
kert