Commit Graph

6 Commits (376e7ffe1965537f91fcf60c128098145a11c3c6)

Author SHA1 Message Date
Martin Kojtal e245c1ecda
Merge pull request #9150 from kjbracey-arm/armc6_fpu
Check correct ARMC6 predefine for FP codegen
2018-12-20 10:47:32 +00:00
Kevin Bracey 91f0be6ac3 Check correct ARMC6 predefine for FP codegen
For ARMC6, CMSIS headers were checking the `__ARM_PCS_VFP`, which
indicates hardfp ABI in use, when they need to check whether FP
code generation is enabled. Change this to `__ARM_FP`, so it
works for platforms using softfp ABI.

Change already present in CMSIS_5 repo, via commit
969822ae162539d50617d1e5a3634ee2fd3b60f6, but redone with local
search-and-replace.
2018-12-19 13:03:11 +02:00
Kevin Bracey f04904c6e8 CM3: Make ACTLR bit definitions conditional
The ACTLR register itself is conditional on chip revision, but its
bit definitions were always defined.

Make the the bit definitions also conditional, so it is possible to
produce portable code that sets DISDEFWBUF if available:

    #ifdef SCnSCB_ACTLR_DISDEFWBUF_Msk
       SCnSCB->ACTLR |= SCnSCB_ACTLR_DISDEFWBUF_Msk;
    #endif

(cherry-picked from CMSIS b2b04dbeece0a046556bfc320bef6b20bef3f16f)
2018-12-13 16:31:53 +02:00
Russ Butler 342841aa0f [CMSIS_5]: Updated to 0b521765 2018-08-25 20:41:00 -05:00
Bartek Szatkowski 8afbd66763 [CMSIS_5]: Updated to 49ac527a 2018-05-14 12:18:20 +01:00
Bartek Szatkowski a03591d6e3 CMSIS/RTX: Update CMSIS and RTX to 22b68c
This includes Cortex A support and directory reshuffle.
2017-11-01 09:25:42 +00:00