Volatile makes no real difference when we're using assembler, or locked
functions, but leaving it off could be more efficient for the basic
loads and stores. So add non-volatile overloads in C++ for them.
Get rid of a volatile, and use atomics to synchronise with the interrupt
routine instead.
Useful as a non-RTOS basic compilation check for the atomics - the
fuller atomic test relies on the RTOS.
These are platform tests, but rely on the RTOS to run multiple threads
to exercise it.
(The atomics are still useful in non-RTOS, to protect against interrupt
handlers, but testing versus other threads is easier. The implementation
is the same either way, so doesn't seem worth testing non-RTOS
specifically).
Reimplement atomic code in inline assembly. This can improve
optimisation, and avoids potential architectural problems with using
LDREX/STREX intrinsics.
API further extended:
* Bitwise operations (fetch_and/fetch_or/fetch_xor)
* fetch_add and fetch_sub (like incr/decr, but returning old value -
aligning with C++11)
* compare_exchange_weak
* Explicit memory order specification
* Basic freestanding template overloads for C++
This gives our existing C implementation essentially all the functionality
needed by C++11.
An actual Atomic<T> template based upon these C functions could follow.
One gets this compiler warning from nvstore.cpp:
```
Compile [ 48.6%]: nvstore.cpp
[Warning] nvstore.cpp@814,9: variable 'os_ret' set but not used [-Wunused-but-set-variable]
```
Turns out it's caused by the fact that the variable is only used
with MBED_ASSERTs, which get optimized out or not, depending on your
build profile. In reality we do not need a separate variable for that
in my opinion though, so we can just use the ret-variable instead
and drop the os_ret variable completely and thus avoid this
compiler warning.
SPI peripherals' asynch transaction buffers are now wrapped by
SingletonPtr, which needs to take the singleton_lock Mutex when first
accessed. If it was first accessed by an asynch transaction started from
IRQ, that would not be possible.
Add a SingletonPtr::get() call to the SPI construction process so that
the peripheral's buffer is fully constructed before any SPI methods can
be called, meaning asynch methods won't fail from IRQ.
(Other pre-existing synchronisation issues with async remain, but this
avoids a new trap in Mbed OS 5.12).
Nanostack eventloop tick timer can be used in case high resolution
platform timer is not needed. One usecase for that is Pelion
Cloud client when using for example cellular connectivity. This enables
PDMC application to enter deep sleep state.
To support block device out of mbed-os tree in KVStore, user needs to:
1. Configure blockdevice to "other".
2. Override get_other_blockdevice() to provide block device out of mbed-os tree.
Only release if the current _connect_status is CONNECTING. If the semaphore is released many times for each connect, then the next connect will not wait(), as it will be able to decrement the semaphore imediatelly.
Purposes:
* Remove MbedOS-specific code from system_psoc6_{cm4,cm0plus}.c
to simplify updates to new PDL version (startup code is part of PDL).
* Unify mbed_sdk_init initialization sequence for both CPU cores.
This change is non-functional, sequence itself is not changed for any
of the PSoC 6 M4/M0 PSA/non-PSA targets.
Socket ID is usually spitted out by the modem, however there are cases
when the modem is actully taken in as an input argument, e.g., in the
case of QUECTEL M26 modem. This minor knit clarifies that the
CellularSocket::id can be an input argument.
* For ARMC6, core types `Cortex-M4` and `Cortex-M7` did not explicitly
add `--fpu=none`, so it defaulted to assuming FPU present. This would
cause a compilation error if the target's cmsis.h had `__FPU_PRESENT`
defined to 0.
* For GCC, `Cortex-M33FE` did not include `+dsp` in the architecture
selection.
* For ARMC5 and ARMC6, `Cortex-M0+` did not pass `M0plus` to the
non-Clang tools.