files .\targets\TARGET_NORDIC\TARGET_NRF5_SDK13\TARGET_MCU_NRF52832\sdk\softdevice\s132\headers\nrf_ble*.h
renamed to .\targets\TARGET_NORDIC\TARGET_NRF5_SDK13\TARGET_MCU_NRF52832\sdk\softdevice\s132\headers\ble*.h
by hand.
As asked by @0xc0170 in PR #3934, we won't be using device_has for indicating RF/Crypto features any longer. RF config options moved to the SL_RAIL lib.json, crypto config options will come with mbedTLS integration.
* Off by one error in the linker scripts reserved one word too little for the vector table
* Re-apply uvisor changes to emlib. To allow uvisor to run, we should make accesses to the romtable through uvisor's secure read gateway
* Copypasta in target name (EFM32PG12, not EFR32PG12)
* Copypasta in the pin definitions (thanks @akselsm)
* Forgot to update PortName for extra ports on MG/PG12
Targets NUCLEO_F429ZI and UBLOX_EVK_ODIN_W2 have 192K RAM.
Heap size in PR #3871 was increased from 48K to 96K as tls-client
example failed with 48K heap. But this resulted in compilation failures
in mbed-client that requires 71K for global/static data.
Hence this PR reduces heap to 64K that minimum required by tls-client
to work. This also meets mbed-client data segment requirements.
In targets.json, add lf_clock_rc_calib_timer_interval and
lf_clock_rc_calib_mode_config setting which are essential when using BLE
In mbed_overrides.c, create valuables instead of doing printf, those
valuables are intended to be used for debugging in runtime.
Currently, there is the issue in register setting into serial_format().
The issue is that parameter for baudrate setting is initialed zero in this function.
In baudrate is less 9600bps, the issue occurs. In baudrate is over 9600, not occurs. When call serial_baud() before serial_format(), baudrate override and set with an incorrect value.
Therefore, I fixed register setting not to set the parameter of baudrate setting in serial_format().
The pwmout driver is very similar for each STM32 family.
The only family specific part is defined in pwmout_device.h file.
It mainly contains few specific information:
- The mapping of PWM/TIMERS to APB1 or APB2 so that we can get the clock
- The clock calculation uses the right APB clock, which was sometimes
not the case before and could have lead to errors in case dividers were
enabled on APB clock settings. This case is now covered.
- Inactivation of inverted support on feaw families
In case the selected frequency is higher than the requested one, it is
better to send a debug warning rather than an blocking error.
In case of such warning, user may need to redefine the clock tree setting
at higher level (reducing peripheral's input clocks during init phase).
Up to now, speed was set for outputs and alternate, but this is
also valid for input configuration.
By default, let's configure high speed.
This is done firts, because speed for some families like F1 is mixed
with Input/Output mode settings, so can be later over-ridden if needed.
Andrzej Puzdrowski
jeromecoutant
Steven Cooreman
Steven Cooreman
Steven Cooreman
bcostm
Mohammad Azim Khan
ccli8
TsungtaWu
TomoYamanaka
Radhika Raghavendran
adustm
Simon Vogl
Głąbek, Andrzej
Laurent MEUNIER
Mike Fiore