Commit Graph

6 Commits (2a4ef3f4640c091c3b8cbe2f62b3616b8282cfe0)

Author SHA1 Message Date
Laurent MEUNIER fd3a3f9de8 STM: SPI: Initialize Rx in spi_master_write
In case Rx is not initiliased its content might be random from stack.
This is causing problem in case of 8 bits read only as the left-side 8 bits
of the returned int value may contain this random byte data. This was for
instance detected when using SDFileSystem Lib.
2017-01-06 13:20:55 +01:00
Laurent MEUNIER e2613d5058 stm32 spi : IRQ handler light optimization
This commit contains a few optimizations to get a better performance
in SPI Asynch mode
2016-11-18 09:59:53 +01:00
Laurent MEUNIER 79af576051 stm32 spi - IRQ management
Disable IRQ when transfer is finished.
Also clear pending IRQ after they have been disabled.
2016-11-18 09:59:53 +01:00
Laurent MEUNIER 446dbe6a0e Clean-up style issues
Fix indentation issues, remove useless comments, correct if/else format
2016-10-13 14:21:02 +02:00
Laurent MEUNIER 661b6adb93 [STM32] spi_master_write - rely on HAL
ASYNCH SPI transfer support has been added based on STM HAL services.
To have both ASYNCH and SYNCH work together, we're also moving the
write API to STM HAL instead of direct registers access.
2016-10-13 14:18:21 +02:00
Laurent MEUNIER 0aeea4950c [STM32] Deploy SPI_ASYNCH to all family
the SPI_ASYNCH feature has been already activated for STM32F4.
This patchset makes it supported on all STM32 families by:
- moving spi_s structure at family level instead of board level
- using the F4 spi_api.c reference implementation and making it a common
stm_spi_api.c file which makes maintenance a lot easier.
- the only part that needs to be implemented for each family is the computation
of the clock frequency input to the spi peripheral which is not the same
accross families. So this is what remains in the spi_api.c of each family.

Because of the introduction of the common file, all the above modifications
needs to be done at once.
2016-10-13 14:18:21 +02:00