ccli8
0c1098483f
[NUC472/M487] Refine flow control code between crypto start and crypto ISR
2018-01-05 09:18:24 +08:00
ccli8
6464649c41
[NUC472/M487] Coordinate crypto interrupt handler among AES/PRNG
2018-01-05 09:18:20 +08:00
ccli8
d66074fecc
[NUC472/M487] Coordinate crypto init among AES/DES/SHA/PRNG
...
Add counter to track crypto init among crypto sub-modules. It includes:
1. Enable crypto clock
2. Enable crypto interrupt
As counter gets zero, crypto clock is disabled to save power.
2018-01-05 09:18:18 +08:00
cyliangtw
d8a9e35a0c
[M487/NUC472] Refine trng_get_bytes for consistency and readability
2017-11-13 12:11:08 +08:00
cyliangtw
2ee058be53
[M487/NUC472] Refine for correctness control
2017-11-10 16:22:35 +08:00
cyliangtw
e252b10148
[M487/NUC472] zeroize random data on the stack memory
2017-11-09 16:01:14 +08:00
cyliangtw
76c2c19853
[M487/NUC472] Unified code-path for remaining bytes of TRNG_Get
2017-11-08 19:56:12 +08:00
cyliangtw
4118afa259
[M487/NUC472] TRN_Get support 32 bytes unalignment
2017-11-08 14:23:05 +08:00
cyliangtw
b55708ec65
[NUC472] remove stray tabs to avoid formatting slips
2017-03-30 09:17:35 +08:00
cyliangtw
c1b8509b23
[NUC472] Enable HW AES
2017-03-23 10:03:58 +08:00
cyliangtw
ec945db013
[NUC472] Resolve TRNG GCC warning
2016-12-13 11:10:51 +08:00
Christopher Haster
0bad622a16
restructure - Moved targets out to top level
...
hal/targets -> targets
hal/targets.json -> targets/targets.json
2016-09-30 19:18:09 -05:00