5 Commits (1d450f82fb065f95fbdc44a3bf3d69a953172bfb)

Author	SHA1	Message	Date
Jaeden Amero	778d6822bf	RTX5: uVisor: Switch threads very carefully ... uVisor doesn't set the PSP of the target thread. The RTOS sets the PSP of the target thread from the target thread's TCB. However, when interrupts of higher priority than PendSV happen between the call to uVisor to switch boxes, and the RTOS setting PSP, the uVisor vIRQ interrupt handler will attempt to use an invalid PSP (the PSP from before the box and thread switch). This leads to a crash. Make box and thread switching atomic by disabling interrupts immediately before the box switching until immediately after the new PSP is set.	2017-06-04 14:41:59 +01:00
Bartosz Szatkowski	39a1b39ce1	Bump number of ARMC mutexes to fix PAL test failure	2017-05-30 18:55:56 +01:00
Yuguo Zou	f03509c6cb	Add up OS_MUTEX_NUM for ARMCC compiler ... CI shield test (SPI test) may need 7 mutexes	2017-05-30 18:55:56 +01:00
Bartek Szatkowski	80cb65e094	Add more verbose RTOS error messages	2017-05-30 18:55:56 +01:00
Bartek Szatkowski	05548e786d	Rename directories rtx->rtx4 rtx2->rtx5	2017-05-30 18:55:55 +01:00