Commit Graph

11 Commits (12536436f8a587acaa92c10dd12bca392738559e)

Author SHA1 Message Date
Bartek Szatkowski a1736e6341 Boot: Provide dynamic mutexes for ARM toolchain
ARM toolchain requires variable number of dynamic mutexes. We use combination of
RTX mutex pool and heap allocation to achieve that.
2017-07-21 10:09:53 +01:00
Kevin Gilbert 4d1ad1d3d5 Fix typo runnig_thread -> running_thread 2017-06-30 17:24:43 -05:00
Bartek Szatkowski 8cc21ea505 RTX: Fixed RTXv5 mutex owner list handling.
The prev-pointer of the running threads mutex list was not set when
multiple mutexes are acquired at a time. This leads to a corrupted list
if the mutexes are not freed in reversed order.

Original commit for CMSIS_5:
commit 729f6ab08540342b7de7612fac103539d5b2f168
Author: Jonatan Antoni <jonatan.antoni@arm.com>
Date:   Wed Apr 19 15:38:43 2017 +0200
2017-06-27 14:39:34 +01:00
Vincent Coubard fd7eff202c RTOS: Allow per target definition of OS_IDLE_THREAD_STACK_SIZE.
The stack required for the idle thread is highly dependent on the
target because it will call the sleep function which is target
specific.

While 256 bytes of stack is enough for most targets, others like the
NRF52840 might require more.

With this change, target maintainers can specify the idle thread stack
size in their mbed_rtx.h file.
2017-06-16 10:11:12 +01:00
Russ Butler fc18250b1f Increase background stack size to fix overflow
Bump the background stack size to 512 bytes to fix stack overflows on
the NRF52 and so it is the same size as it was before the switch to
RTX5.
2017-06-14 17:31:52 -05:00
Jimmy Brisson fc6c2b85ff Upcase assembly file suffix for preprocesssing 2017-06-09 00:03:23 -05:00
Jaeden Amero 778d6822bf RTX5: uVisor: Switch threads very carefully
uVisor doesn't set the PSP of the target thread. The RTOS sets the PSP
of the target thread from the target thread's TCB. However, when
interrupts of higher priority than PendSV happen between the call to
uVisor to switch boxes, and the RTOS setting PSP, the uVisor vIRQ
interrupt handler will attempt to use an invalid PSP (the PSP from
before the box and thread switch). This leads to a crash. Make box and
thread switching atomic by disabling interrupts immediately before the
box switching until immediately after the new PSP is set.
2017-06-04 14:41:59 +01:00
Bartosz Szatkowski 39a1b39ce1 Bump number of ARMC mutexes to fix PAL test failure 2017-05-30 18:55:56 +01:00
Yuguo Zou f03509c6cb Add up OS_MUTEX_NUM for ARMCC compiler
CI shield test (SPI test) may need 7 mutexes
2017-05-30 18:55:56 +01:00
Bartek Szatkowski 80cb65e094 Add more verbose RTOS error messages 2017-05-30 18:55:56 +01:00
Bartek Szatkowski 05548e786d Rename directories rtx->rtx4 rtx2->rtx5 2017-05-30 18:55:55 +01:00