Corrected PPP thread stack size for RZ_A1_EMAC, CYW943012P6EVB_01,
CY8CPROTO_062_4343W, CY8CKIT_062_WIFI_BT and CY8CKIT_062S2_43012
that have special configuration for PPP thread size. Removed
pppInterface() helper call from network interface. It causes binary
compatibility break with precompiled network interface classes. Call
is helper function to check network interface type in case it is
unknown, and is not mandatory or used with PPP.
If PPP interface is the lwIP default interface, adds the PPP DNS
servers to default DNS server storage. If PPP is not default
interface, then adds DNS servers to interface specific storage.
Created (a new) PPP interface for PPP service. Removed lwip
dependencies to PPP (memory allocations etc.). Moved PPP
configuration options away from lwIP mbed_lib.json to new
PPP service. For backwards compatibility, using the old
options is also currently supported.
PPP service encapsulates the PPP protocol. PPP interface can be used as
helper class to bind PPP protocol with network stack (similar to
EMAC and L3IP interface). Added PPP interface to onboard network
stack class.
Created PPP service class that encapsulates the PPP protocol.
Class is similar to EMAC and L3IP classes with additional methods
to read IP and DNS server addresses negotiation using PPP and
to set PPP specific parameters (file handle for modem access etc.).
PPP service can use on its own thread or in run in mbed os event
Queue thread.
Added ppp_nsapi.cpp module that implements the nsapi_ppp.h
services.
Added ppp_nsapi.cpp module that implements the nsapi_ppp.h
services.
Fix SPI module index error in modidx_ns_tab table in CLK_SetModuleClock_S().
Need to update secure image for this bugfix.
This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-spi/
SPI - init/free test all pins.
M451 series can classify by M45xD/M45xC and M45xG/M45xE. To support this
classification:
1. Create TARGET_M45xD_M45xC and TARGET_M45xG_M45xE targets.
2. Mark NUMAKER_PFM_M453 belongs to TARGET_M45xG_M45xE by 'extra_labels_add'
in targets.json.
3. Fix pin name table according to the classification.
4. Fix pinmap table according to the classification.
MOSI1/MISO1 are used in second bit of 2-bit transfer mode and cannot be used
for normal MOSI/MISO. Remove them from pinmap.
This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-spi/
SPI - basic test.
Without free-up of peripheral pins, peripheral pins of the same peripheral may
share by multiple ports after port iteration, and this peripheral may fail with
pin interference.
In Nuvoton, only new-design chips support GPIO input pull-high/pull-low modes.
Targets not supporting this feature are listed below:
- NUMAKER_PFM_NANO130
- NUMAKER_PFM_NUC472
- NUMAKER_PFM_M453
Veijo Pesonen
Michal Paszta
Mahesh Mahadevan
Dominika Maziec
aqib-ublox
Teppo Järvelin
Martin Kojtal
Mika Leppänen
Kari Haapalehto
Chun-Chieh Li