By default QSPIFBlockDevice assumes a Flash memory have two Status registers and when writing the Status registers it writes 2 bytes using the WRSR instruction. This will not work on a ISSI Flash memory as they only have a single status register and attempting to write two bytes using WRSR will cause it to ignore the request and be unable to set the QE bit.
ISSI datasheet specifies that the WRSR instruction only write a single byte so override the number of status registers for ISSI Flash memories.
After switching from local variables to shared info structure JEDEC
Basic Flash Parameter Table and Sector Map Parameter Table addresses
and sizes must be protected by a mutex. Theoretically multiple calls
to Q/SPIFBlockDevice might occur.
This far all SFDP Sector Map Table related data has been found in small
pieces inside QSPIFBlockDevice. Purpose was to consolidate the data
under one SFDP structure where all the information gathered from
SFDP tables is stored.
Parsing a Sector Map Table was made more generic so that later it can be
moved under SFDP module. Once that is done it can be shared with
SPIFBlockDevice to avoid code duplication.
Separates SFDP header retrieval and moves it as a part of the earlier
introduced SFDP file.
Purpose is to abstract away differences between SPIF and QSPIF devices
when it comes to fetching the SFDP headers from a device.
4-byte addressing has been seen to cause failures on NORDIC
boards and with Macronix memories. Suppress the attempt to enable it
on that hardware (via vendor quirks and a target check) until either
the failure cause can be fixed or a more robust suppression mechanism
is implemented.
Use a vendor id check to only perform this enable on devices which define the
second configuration register where the fast mode enable bit lives.
Change _enable_fast_mode to use the standard status register reading and writing functions
Default to 2 status registers, but update this value if necessary
during vendor quirk handling for parts (currently only Macronix)
which have one status register and two control registers. For the
purposes of QSPIFBlockDevice, these are all considered status
(or at least "status-like") registers because they are all written
via the Write Status Register instruction.
Set the custom RDCR instruction for Macronix during quirk handling.
Update reading and writing of status registers to handle a variable
number of status registers.
Introduce a separate function for handling alterations to device interaction
which are not covered by the SFDP tables and therefore require checking against
the vendor id.
QSPIFBlockDevice::_clear_block_protection() has logic to retain the
WIP and WEL bits in status register 1, but it failed to account for
the situation where the QE bit is also in status register 1.
In _sfdp_set_quad_enabled, note the status register and bit therein
for the quad enable, so that _clear_block_protection can retain it.
This function writes a "config" register to ensure that the flash part
is in high performance mode, not low-power mode. This is required at
by at least MX25R6435F in order to operate at frequencies > 33MHz
(for reference, DISCO_L475VG_IOT01A runs the QSPI interface at 80 MHz).
The config register that this writes does not appear to be covered by
the SFDP spec (JESD216D.01) so this remains the status quo of
unconditional execution, as has been done on master since #8352.
Uruloke
Veijo Pesonen
Martin Kojtal
Anna Bridge
Michal Paszta
Kyle Kearney
Matthew Macovsky