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5 Commits (mbed-os-6.11.0-docs-utf-8-fix)

Author SHA1 Message Date
Chun-Chieh Li 8df96ec50a Nuvoton: Make SPI inter-frame (delay match configured suspend interval 
In no MISO case, skip SPI read so that no more write/read delay contribute to SPI inter-frame delay when data is written successively.

Update targets:
-   NUMAKER_PFM_NANO130
-   NUMAKER_PFM_NUC472
-   NUMAKER_PFM_M453
-   NUMAKER_PFM_M487/NUMAKER_IOT_M487
-   NU_PFM_M2351_*
-   NUMAKER_IOT_M263A
-   NUMAKER_M252KG
 2020-02-17 15:00:09 +08:00
Chun-Chieh Li 967effe59f [M252KG] Free up peripheral pins in peripheral free-up HAL API 
Without free-up of peripheral pins, peripheral pins of the same peripheral may
share by multiple ports after port iteration, and this peripheral may fail with
pin interference.
 2019-09-27 17:45:56 +08:00
Chun-Chieh Li d9217ed77a [M252KG] Fix redundant SPI clock generation 
Fix SPI clocks are generated redundantly at the end of transfer.

This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-spi/
SPI - async mode.
 2019-09-27 17:45:55 +08:00
Chun-Chieh Li 0917a0d5a6 [M252KG] Fix IP initialization sequence 
Better IP initialization sequence:
1. Configure IP pins
2. Select IP clock source and then enable it
3. Reset the IP (SYS_ResetModule)

NOTE1: IP reset takes effect regardless of IP clock. So it doesn't matter if
       IP clock enable is before IP reset.
NOTE2: Non-configured pins may disturb IP's state, so IP pinout first and then
       IP reset.
NOTE3: IP reset at the end of IP initialization sequence can cover unexpected
       situation.
 2019-09-27 17:45:54 +08:00
Chun-Chieh Li 36278618ad Support Nuvoton's NUMAKER_M252KG target 2019-09-27 17:45:52 +08:00